Thesis (M.S. in Information Systems and Operations)--Naval Postgraduate School, March 2003. / Thesis advisor(s): Alex Bordetsky, Randy J. Hess. Includes bibliographical references (p. 101-105). Also available online.

Thesis (M.S.)--Brigham Young University. Dept. of Electrical and Computer Engineering, 2003. / Includes bibliographical references (p. 65-66).

Thesis (Ed. D.)--West Virginia University, 2003. / Title from document title page. Document formatted into pages; contains vi, 142 p. : ill. Vita. Includes abstract. Includes bibliographical references (p. 100-110).

The advent of serial tera-bit telecommunication and multi-gigahertz I/O interfaces is posing challenges on the semiconductor and ATE industries. There is a gap in signal integrity testing between what has been specified in serial link standards and what can be practically tested in production. A thorough characterization and a more cost-effective test of the signal integrity, such as BER, jitter, and eye margin, are critical to identify and isolate the root cause of the system degradation and to the binning in production. In this dissertation, measurement and testing schemes on signal integrity are explored. A solution for diagnosing jitter and predicting the range of consequent BER is proposed. This solution is applicable to decomposition of correlated and uncorrelated jitter in both clock and data signals. The statistical information of jitter is estimated using TLC functions. TLC treats jitter in its original form, as a time series, resulting in good accuracy in the decomposition. Hardware results in a PLL indicate that the approach is still valid when the traditional histogram-based method fails. This approach can be implemented using only one-shot capture instead of multiple captures to average out the uncorrelated jitter from the correlated jitter. Therefore, the TLC functions enable test time reduction in jitter decomposition compared to traditional averaging methods. Hardware measurements on stressed data signals are presented to validate the proposed technique. We have also explored low cost, high bandwidth techniques using Built In Self Test(BIST) for on-chip jitter measurement. Undersampling provides a lowcost test solution for on-chip jitter measurement. However, it suffers from sampling clock phase error and time quantization noise. These timing uncertainties on the test accuracy of the traditional technique using a single channel structure can be alleviated by extracting the correlation between two channels using a single reference clock. Simulation results indicate that the proposed approach can achieve a better measurement accuracy and a higher degree of tolerance to sampling clock uncertainty and quantization error than does the single-channel structure, with little additional test overhead. TIADCs provide an attractive solution to the realization of analog front ends in high speed communication systems,such as 10GBASE-T and 10GBASEFiber. However, gain mismatch, offset mismatch, and sampling time mismatch between time-interleaved channels limit the performance of TIADCs. A low-cost test scheme is developed to measure timing mismatch using an undersampling clock. This method is applicable to an arbitrary number of channels, achieving picosecond resolution with low power consumption. Simulation results and hardware measurements on a 10GSps TIADC are presented to validate the proposed technique. / text

published_or_final_version / Electrical and Electronic Engineering / Doctoral / Doctor of Philosophy

published_or_final_version / Electrical and Electronic Engineering / Doctoral / Doctor of Philosophy

Clock synchronization for Wireless Sensor Networks (WSNs) has attracted lots of attention due to its importance for operations in WSNs. In traditional centralized clock synchronization algorithms, all the local information should be transmitted to a fusion center for processing, and the results need to be forwarded back to each individual sensor, thus resulting in a heavy burden on communication and computation in the network. In addition, it also lacks of adaptability to link failures and dynamic changes in the network topology, which greatly prevents their use in WSNs. Hence, in this thesis, we focus on developing energy-efficient distributed clock synchronization algorithms for WSNs. Firstly, global clock synchronization problem is investigated with time-varying clock parameters (skew and offset) owing to imperfect oscillator circuits. A distributed Kalman filter is developed for clock parameters tracking. The proposed algorithm only requires each node to exchange limited information with its direct neighbors, thus is energy efficient, scalable with network size, and is robust against changes in network connectivity. A low-complexity distributed algorithm based on Coordinate-Descent with Bootstrap (CD-BS) is also proposed to provide rapid initialization of the tracking algorithm. Simulation results show that the proposed distributed tracking algorithm achieves the long-term accuracy for the clock parameters close to the Bayesian Cramer-Rao Lower Bound. Secondly, the problem of global clock synchronization for WSNs in the presence of unknown exponential delays is studied. The joint maximum likelihood estimator of clock offsets, clock skews and fixed delays of the network is first formulated as a global linear programming (LP) problem. Based on the Alternating Direction Method of Multipliers (ADMM), we propose a fully-distributed synchronization algorithm that has low communication overhead and computation cost. Simulation results show that the proposed algorithm achieves better accuracy than consensus algorithm and the distributed least squares algorithm, and can always converge to the centralized optimal solution. Finally, global clock synchronization for WSNs under the exponentially distributed delays is re-visited with the fast convergence min-sum algorithm. The synchronization problem is cast into an optimization problem represented by factor graph, and a closed-form expression of the messages passed between nodes are derived. Simulation results show that this distributed algorithm can approach the centralized LP solution with faster convergence speed compared to ADMM-based algorithm. / published_or_final_version / Electrical and Electronic Engineering / Doctoral / Doctor of Philosophy

Not available / text

Not available / text

Not available / text