The scaling down of transistor sizes has imposed significant challenges in today's technology. Memories such as eDRAM, are experiencing poor retention time because of challenges such as reference voltage variation, high transistor leakage, and low cell capacitance. It can be seen that we must consider not only the first order effects, but also the second order effects to ensure we keep up with current technology trends such as Moore's law. In this thesis we explore various circuit level techniques on level shifters in order to achieve better retention time. With our research, we have addressed important design challenges and propose techniques that can be utilized in current and emerging technologies. Level shifters (LS) are crucial components in low-power design where the die is segregated in multiple voltage domains. LS are used at the voltage domain interfaces to mitigate sneak path current. A less-known but very important application of LS is in high voltage drivers for designs where voltage boosting is needed for performance and functionality. We first study LS in eDRAM where LS is employed in the wordline path. Our investigation reveals that leakage power of LS can pose a serious threat by lowering the wordline voltage and subsequently affecting the speed and retention time of the eDRAM. It can also be noted that the delay of the LS under worse case process corners can cause significant functional discrepancies. We propose low-power pulsed-LS with supply gating to circumvent these issues. Our analysis indicate that pulsed-LS design can improve the worst case speed from 2.7%-43%. We extended this concept to design generic self-collapsible LSs that can be used for other applications such as voltage interfaces. The self-collapsed design in both applications improved the worst case speed from 6%-24% and 89% in some cases.

Embedded SRAM memory is a vital component in modern SoCs. More than 80% of the System-on-Chip (SoC) die area is often occupied by SRAM arrays. As such, system reliability and yield is largely governed by the SRAM's performance and robustness. The aggressive scaling trend in CMOS device minimum feature size, coupled with the growing demand in high-capacity memory integration, has imposed the use of minimal size devices to realize a memory bitcell. The smallest 6T SRAM bitcell to date occupies a 0.1um2 in silicon area. SRAM bitcells continue to benefit from an aggressive scaling trend in CMOS technologies. Unfortunately, other system components, such as interconnects, experience a slower scaling trend. This has resulted in dramatic deterioration in a cell's ability to drive a heavily-loaded interconnects. Moreover, the growing fluctuation in device properties due to Process, Voltage, and Temperature (PVT) variations has added more uncertainty to SRAM operation. Thus ensuring the ability of a miniaturized cell to drive heavily-loaded bitlines and to generate adequate voltage swing is becoming challenging. A large percentage of state-of-the-art SoC system failures are attributed to the inability of SRAM cells to generate the targeted bitline voltage swing within a given access time. The use of read-assist mechanisms and current mode sense amplifiers are the two key strategies used to surmount bitline loading effects. On the other hand, new bitcell topologies and cell supply voltage management are used to overcome fluctuations in device properties. In this research we tackled conventional 6T SRAM bitcell limited drivability by introducing new integrated voltage sensing schemes and current-mode sense amplifiers. The proposed schemes feature a read-assist mechanism. The proposed schemes' functionality and superiority over existing schemes are verified using transient and statistical SPICE simulations. Post-layout extracted views of the devices are used for realistic simulation results. Low-voltage operated SRAM reliability and yield enhancement is investigated and a wordline boost technique is proposed as a means to manage the cell's WL operating voltage. The proposed wordline driver design shows a significant improvement in reliability and yield in a 400-mV 6T SRAM cell. The proposed wordline driver design exploit the cell's Dynamic Noise Margin (DNM), therefore boost peak level and boost decay rate programmability features are added. SPICE transient and statistical simulations are used to verify the proposed design's functionality. Finally, at a bitcell-level, we proposed a new five-transistor (5T) SRAM bitcell which shows competitive performance and reliability figures of merit compared to the conventional 6T bitcell. The functionality of the proposed cell is verified by post-layout SPICE simulations. The proposed bitcell topology is designed, implemented and fabricated in a standard ST CMOS 65nm technology process. A 1.2_ 1.2 mm2 multi-design project test chip consisting of four 32-Kbit (256-row x 128-column) SRAM macros with the required peripheral and timing control units is fabricated. Two of the designed SRAM macros are dedicated for this work, namely, a 32-Kbit 5T macro and a 32-Kbit 6T macro which is used as a comparison reference. Other macros belong to other projects and are not discussed in this document.

Embedded SRAM memory is a vital component in modern SoCs. More than 80% of the System-on-Chip (SoC) die area is often occupied by SRAM arrays. As such, system reliability and yield is largely governed by the SRAM's performance and robustness. The aggressive scaling trend in CMOS device minimum feature size, coupled with the growing demand in high-capacity memory integration, has imposed the use of minimal size devices to realize a memory bitcell. The smallest 6T SRAM bitcell to date occupies a 0.1um2 in silicon area. SRAM bitcells continue to benefit from an aggressive scaling trend in CMOS technologies. Unfortunately, other system components, such as interconnects, experience a slower scaling trend. This has resulted in dramatic deterioration in a cell's ability to drive a heavily-loaded interconnects. Moreover, the growing fluctuation in device properties due to Process, Voltage, and Temperature (PVT) variations has added more uncertainty to SRAM operation. Thus ensuring the ability of a miniaturized cell to drive heavily-loaded bitlines and to generate adequate voltage swing is becoming challenging. A large percentage of state-of-the-art SoC system failures are attributed to the inability of SRAM cells to generate the targeted bitline voltage swing within a given access time. The use of read-assist mechanisms and current mode sense amplifiers are the two key strategies used to surmount bitline loading effects. On the other hand, new bitcell topologies and cell supply voltage management are used to overcome fluctuations in device properties. In this research we tackled conventional 6T SRAM bitcell limited drivability by introducing new integrated voltage sensing schemes and current-mode sense amplifiers. The proposed schemes feature a read-assist mechanism. The proposed schemes' functionality and superiority over existing schemes are verified using transient and statistical SPICE simulations. Post-layout extracted views of the devices are used for realistic simulation results. Low-voltage operated SRAM reliability and yield enhancement is investigated and a wordline boost technique is proposed as a means to manage the cell's WL operating voltage. The proposed wordline driver design shows a significant improvement in reliability and yield in a 400-mV 6T SRAM cell. The proposed wordline driver design exploit the cell's Dynamic Noise Margin (DNM), therefore boost peak level and boost decay rate programmability features are added. SPICE transient and statistical simulations are used to verify the proposed design's functionality. Finally, at a bitcell-level, we proposed a new five-transistor (5T) SRAM bitcell which shows competitive performance and reliability figures of merit compared to the conventional 6T bitcell. The functionality of the proposed cell is verified by post-layout SPICE simulations. The proposed bitcell topology is designed, implemented and fabricated in a standard ST CMOS 65nm technology process. A 1.2_ 1.2 mm2 multi-design project test chip consisting of four 32-Kbit (256-row x 128-column) SRAM macros with the required peripheral and timing control units is fabricated. Two of the designed SRAM macros are dedicated for this work, namely, a 32-Kbit 5T macro and a 32-Kbit 6T macro which is used as a comparison reference. Other macros belong to other projects and are not discussed in this document.

Abstract Four high-performance circuits design techniques for embedded DRAM are proposed. First, a negative voltage generator having high efficiency is proposed to provide the negative voltage for the modified word line driver. The negative voltage generator circuits could be manufactured in n-Well CMOS process, and its operation achieve optimal output voltage. When 2.0-V supplied voltage is applied, the output voltage of -1.6-V is obtained. Even though, the supplied voltage is scaled down to 1.5-V, the output voltage can still achieve -1.05-V. In contrast, the output voltage of traditional one under 2.0-V supplied voltage is only -0.67-V. Second, a fast wordline driver suitable for PMOS pass transistor is proposed. The wordline driver improves the turned-on time by 26.8ns compared with the traditional one and raises the operating speed by 79%. Third, a new reduced clock-swing driver is proposed. Under 2.0-V supplied voltage and 100MHz operating frequency, the total power consumption of the new driver working with RCSFF is reduced by 10% than that of traditional one working with RCSFF. For the above advantage of low power, the new driver is thus more suitable for embedded DRAM applications. Fourth, a modified hierarchical read bus amplifier is proposed. The read bus amplifier is based on the new sense-amplifier. It could drive the output by full-swing voltage. It improves the sensing speed by 2.1ns. And it got the same advantage of no dc idling current as the traditional N&PMOS cross-coupled amplifier. In this thesis, finally, the performance of these circuits is also integrated and examined in an 1-Kbit embedded DRAM test circuit. The simulation RAS access time of 27.9ns is achieved under 2.0V supplied voltage and loading of 16-Mbit embedded DRAM. This indicated the above proposed circuits could be applied in the low voltage and high speed embedded DRAM.

Indiana University-Purdue University Indianapolis (IUPUI) / In this dissertation, a beyond-CMOS approach to Static Random Access Memory (SRAM) design is investigated using exploratory transistors including Tunnel Field Effect Transistor (TFET), Carbon Nanotube Field Effect Transistor (CNFET) and Graphene NanoRibbon Field Effect Transistor (GNRFET). A Figure-of-Merit (FOM) based comparison of 6-transistor (6T) and a modified 8-transistor (8T) single-port SRAMs designed using exploratory devices, and contemporary devices such as a FinFET and a CMOS process, highlighted the performance benefits of GNRFETs and power benefits of TFETs. The results obtained from the this work show that GNRFET-based SRAM have very high performance with a worst-case memory access time of 27.7 ps for a 16x4-bit 4-word array of 256-bitcells. CNFET-based SRAM bitcell consume the lowest average power during read/write simulations at 3.84 uW, while TFET-based SRAM bitcell show the best overall average and static power consumption at 4.79 uW and 57.8 pW respectively. A comparison of these exploratory devices with FinFET and planar CMOS showed that FinFET-based SRAM bitcell consumed the lowest static power at 39.8 pW and CMOS-based SRAM had the best read, write and hold static noise margins at 201 mV, 438 mV and 413 mV respectively. Further, the modification of 8T-SRAMs via dual wordlines for individually controlling read and write operations for uni-directional transistors TFET and CNFET show improvement in read static noise margin (RSNM). In dual wordline CNFET 8T-SRAM, an RSNM improvement of approximately 23.6x from 6 mV to 142 mV was observed by suppressing the read wordline (RWL) from a nominal supply of 0.71 V down to 0.61 V. In dual wordline TFET 8T-SRAM, an RSNM improvement of approximately 16.2x from 5 mV to 81 mV was observed by suppressing the RWL from a nominal supply of 0.6 V down to 0.3 V. Next, the dissertation explores whether the robustness of SRAM arrays can be improved. Specifically, the robustness related to noise margin during the write operation was investigated by implementing a negative bitline (NBL) voltage scheme. NBL improves the write static noise margin (WSNM) of the SRAM bitcells in the row of the array to which the data is written during a write operation. However, this may cause degraded hold static noise margin (HSNM) of un-accessed cells in the array. Applying a negative wordline voltage (NWL) on un-accessed cells during NBL shows that the NWL can counter the degraded HSNM of un-accessed cells due to NBL. The scheme, titled as NBLWL, also allows the supply of a lower NBL, resulting in higher WSNM and write-ability benefits of accessed row. By applying a complementary negative wordline voltage to counter the half-select condition in columns, the WSNM of cells in accessed rows was boosted by 10.9% when compared to a work where no negative bitline was applied. In addition, the HSNM of un-accessed cells remain the same as in the case where no negative bitline was implemented. Essentially, a 10.9% boost in WSNM without any degradation of HSNM in un-accessed cells is observed. The dissertation also focuses on the impact of process-related variations in SRAM arrays to correlate and characterize silicon data to simulation data. This can help designers remove pessimistic margins that are placed on critical signals to account for expected process variation. Removing these pessimistic margins on critical data paths that dictate the memory access time results in performance benefits for the SRAM array. This is achieved via an in-situ silicon monitor titled SRAM process and ageing sensor (SPAS), which can be used for silicon and ageing characterization, and silicon debug. The SPAS scheme is based on a process variation tolerant technique called RAZOR that compares the data arriving on the output of the sense amplifiers during the read operation. This scheme can estimate the impact of process variation and ageing induced slow-down on critical path during read operation of an array with high accuracy. The estimation accuracy in a commercially available 65nm CMOS technology for a 16x16 array at TT, and global SS and FF corners at nominal supply and testing temperature were found to be 99.2%, 94.9% and 96.5% respectively. Finally, redundant columns, an architectural-level scheme for tolerating failing SRAM bitcells in arrays without compromising performance and yield, is studied. Redundant columns are extra columns that are programmed when bitcells in the regular columns of an array are slower or have higher leakage than expected post-silicon. The regular columns are often permanently disabled and remain unused for the chip lifetime once redundant columns are enabled. In the SRRC scheme proposed in this thesis, the regular columns are only temporarily disabled, and re-used at a later time in chip life cycle once the previously awakened redundant columns become slower than the disabled regular columns. Essentially, the scheme can identify and temporarily disable the slowest column in an array until other mitigating factors slow down active columns. This allows the array to operate at a memory access time closer to the target access time regardless of other mitigating factors slowing down bitcells in arrays during chip life cycle. An approximate 76.4% reduction in memory access time was observed from a 16x16 array from simulations in a commercially available 65nm CMOS technology with respect to a work where no redundancy was employed.