This diploma thesis focuses on the High-level synthesis (HLS). The first part deals with theoretical details and methods that are used in HLS tools. This is followed by a description of the synthesis tool Vivado HLS which will be used for implementation of an application. In the second part is briefly introduced high dynamic range images (HDR) and tone mapping. The third part is dedicated to design and implementation of the aplication which implements tone mapping methods in HDR images. This methods are implemented in Vivado HLS and language C++. This application is based on platform Xilinx Zynq and it uses multiexposure camera for capturing HDR images. Images are transmitted to FPGA for tone mapping processing.

Traditional hardware radios provide very rigid solutions to radio problems. Intelligent software defined radios, also known as cognitive radios, provide flexibility and agility compared to hardware radio systems. Cognitive radios are well suited for radio applications in a changing radio frequency environment, such as dynamic spectrum access. In this thesis, a cognitive radio is demonstrated where the system self reconfigures to demodulate a detected waveform. The GNU Radio framework is used to provide basic software defined radio building blocks and is supplemented with FPGA accelerators. The use of GNU Radio compliant hardware interfaces allows for seamless hardware/software radio deployments. Dynamic resource mapping allows radio designers to operate at a layer of abstraction above the physical radio implementation. By establishing lower level abstraction layers, future researchers can focus on larger picture concepts such as learning algorithms and behavioral models for the cognitive engine. / Master of Science

This work describes using High-Level Synthesis in image processing application. The application is for Xilinx ZYNQ platform. The source code of components for FPGA is written in C++ programming language. For High-Level Synthesis is used Xilinx Vivado HLS tool. In the application are designed and implemented Sobel filter, Median filter, Bilateral filter and architecture for AdaBoost classificator. The extension of this work is implemented the component for network traffic. The component finds the begin of the packet.

The common availability of multiple processors in modern CPU devices and the need to reduce cost of embedded systems has created a drive for integrating functionalities from different parts of a system into a single Multi- Processor System-on-Chip (MPSoC) device. As a result, system resources are shared amongst the critical and non-critical components of the system, which results in a mixed-criticality system (MCS). An example of a MCS is to combine an airbag control unit with the infotainment system of a car, in such a case, both components must be certified unless an isolation mechanism that can prevent the non-critical to interfere with the critical subsystems is implemented. This isolation can be achieved via spatial and temporal partitioning of system resources, such as static mapping of CPUs to critical tasks, memory and IO virtualization, and time domain multiplexing of applications. System isolation is currently achievable through virtualization techniques, and is commonly used in data centers and personal computers. Recently, virtualization solutions have been emerging for embedded systems in order to cope with the increased design complexity, the stringent non-functional requirements, and to facilitate the certification process of MCS. The achieved performance, safety, security, and robustness in a virtualized system depends on the virtualization architecture and hardware platform. This thesis work performs state-of the art research in the field of mixedcriticality embedded systems with a focus on virtualization of embedded systems. As a result, a deep study of virtualization architectures, and open-source virtualization solutions is conducted in order to understand the consequences of using this technology in MCS. The work is concluded with a design and implementation of mixed-criticality embedded system that leverages the hardware capabilities of the target device (Zynq-7000 all programmable SoC), and contributes to the Living Lab WP7 of the EMC2 project.

Modern radar technology relies heavily on digital signal processing. As radar technology pushes the boundaries of miniaturization, computational systems must be developed to support the processing demand. One particular application for small radar technology is in modern drone systems. Many drone applications are currently inhibited by safety concerns of autonomous vehicles navigating shared airspace. Research in radar based Detect and Avoid (DAA) attempts to address these concerns by using radar to detect nearby aircraft and choosing an alternative flight path. Implementation of radar on small Unmanned Air Vehicles (UAV), however, requires a lightweight and power efficient design. Likewise, the radar processing system must also be small and efficient.This thesis presents the design of the processing system for a small Frequency Modulated Continuous Wave (FMCW) phased array radar. The radar and processing is designed to be light-weight and low-power in order to fly onboard a UAV less than 25 kg in weight. The radar algorithms for this design include a parallelized Fast Fourier Transform (FFT), cross correlation, and beamforming. Target detection algorithms are also implemented. All of the computation is performed in real-time on a Xilinx Zynq 7010 System on Chip (SoC) processor utilizing both FPGA and CPU resources.The radar system (excluding antennas) has dimensions of 2.25 x 4 x 1.5 in3, weighs 120 g, and consumes 8 W of power of which the processing system occupies 2.6 W. The processing system performs over 652 million arithmetic operations per second and is capable of performing the full processing in real-time. The radar has also been tested in several scenarios both airborne on small UAVs as well as on the ground. Small UAVs have been detected to ranges of 350 m and larger aircraft up to 800 m. This thesis will describe the radar design architecture, the custom designed radar hardware, the FPGA based processing implementations, and conclude with an evaluation of the system's effectiveness and performance.

Tato práce se zabývá výběrem vhodného obrazového snímače pro použití v kameře snímající rostliny ve vysokém rozlišení a návrhem vhodného obvodu pro propojení vybraného snímače (SONY IMX253) s vývojovou deskou Avnet MicroZed. Tato práce pojednává o jednotlivých parametrech obrazových snímačů podle kterých je vybírán vhodný obrazový snímač. Je vysvětlen proces výběru vhodného obrazového snímače a podrobněji popsány parametry vybraného snímače. Je naznačena problematika návrhu elektroniky a plošných spojů z hlediska požadavků vysokorychlostních obvodů a citlivých a specifických součástek jako je obrazový snímač. Je nastíněna konfigurace a programování obvodu Xilinx Zynq a nakonec je provedeno zjednodušené teoretické ověření funkčnosti navrženého modulu.

Modern radar technology relies heavily on digital signal processing. As radar technology pushes the boundaries of miniaturization, computational systems must be developed to support the processing demand. One particular application for small radar technology is in modern drone systems. Many drone applications are currently inhibited by safety concerns of autonomous vehicles navigating shared airspace. Research in radar based Detect and Avoid (DAA) attempts to address these concerns by using radar to detect nearby aircraft and choosing an alternative flight path. Implementation of radar on small Unmanned Air Vehicles (UAV), however, requires a lightweight and power efficient design. Likewise, the radar processing system must also be small and efficient. This thesis presents the design of the processing system for a small Frequency Modulated Continuous Wave (FMCW) phased array radar. The radar and processing is designed to be light-weight and low-power in order to fly onboard a UAV less than 25 kg in weight. The radar algorithms for this design include a parallelized Fast Fourier Transform (FFT), cross correlation, and beamforming. Target detection algorithms are also implemented. All of the computation is performed in real-time on a Xilinx Zynq 7010 System on Chip (SoC) processor utilizing both FPGA and CPU resources. The radar system (excluding antennas) has dimensions of 2.25 x 4 x 1.5 in3, weighs 120 g, and consumes 8 W of power of which the processing system occupies 2.6 W. The processing system performs over 652 million arithmetic operations per second and is capable of performing the full processing in real-time. The radar has also been tested in several scenarios both airborne on small UAVs as well as on the ground. Small UAVs have been detected to ranges of 350 m and larger aircraft up to 800 m. This thesis will describe the radar design architecture, the custom designed radar hardware, the FPGA based processing implementations, and conclude with an evaluation of the system's effectiveness and performance.

Abstract This thesis focuses on two important challenges in wireless downlink transmission: multi-user (MU) precoder design and scheduling of users over time, frequency, and spatial resources at any given instant. Data streams intended for different users are transmitted by a multiple-input multiple-output (MIMO) multi-antenna orthogonal frequency division multiplexing (OFDM) system. The transmit precoders are designed jointly across space-frequency resources to minimize the number of backlogged packets waiting at the coordinating base stations (BSs), thereby implicitly performing user scheduling. Then the problem of multicast beamformer design is considered wherein a subset of users belonging to a multicasting group are served by a common group-specific data. The design objective is to either minimize the transmit power for a guaranteed quality-of-service, or to maximize the minimum achievable rate among users for a given transmit power. Unlike existing techniques, the proposed design utilizes both the spatial and frequency resources jointly while designing multi-group beamformers. As an extension to coordinated precoding, the problem of beamformer design for cloud radio access network is considered wherein beamformers are designed centrally, quantized and sent along with data to the respective BSs via backhaul. Since the users can be served by multiple BSs, beamformer design becomes a nonconvex combinatorial problem. Unlike existing solutions, beamformer overhead is also included in the backhaul utilization along with the associated data. As the number of antennas increases, backhaul utilization is dominated by the beamformers. Thus, to reduce the overhead, two techniques are proposed: varying the quantization precision, and reducing the number of active antennas used for transmission. Finally, to reduce the complexity involved in the design of joint space- frequency approach, a two-step procedure is proposed, where a MU-MIMO scheduling algorithm is employed to find a subset of users for each scheduling block. The precoders are then designed only for the chosen users, thus reducing the complexity without compromising much on the throughput. In contrast to the null-space-based existing techniques, a low-complexity scheduling algorithm is proposed based on vector projections. The real-time performance of all the schedulers are evaluated by implementing them on both Xilinx ZYNQ-ZC702 system-on-chip (SoC) and TI TCI6636K2H multi-core SoC. / Tiivistelmä Tässä väitöskirjassa keskitytään kahteen tärkeään langattoman tiedonsiirron haasteeseen alalinkkilähetyksissä: usean käyttäjän (MU) esikooderisuunnitteluun ja käyttäjien skedulointiin aika-, taajuus- ja tilaresurssien yli. Eri käyttäjille tarkoitettuja datavirtoja lähetetään käyttämällä monitulo-monilähtötekniikkaa (MIMO) yhdistettynä monikantoaaltomodulointiin (OFDM). Lähettimien esikooderit suunnitellaan yhteisesti tila- ja taajuusresurssien yli, jotta keskenään yhteistoiminnallisten tukiasemien jonossa olevien pakettien määrää voitaisiin minimoida samalla kun tehdään epäsuorasti käyttäjien skedulointia. Tämän jälkeen työssä paneudutaan monilähetysten (multicast) keilanmuodostussuunnitteluun, jossa monilähetysryhmään kuuluvien käyttäjien alijoukolle lähetetään yhteistä ryhmäspesifistä dataa. Suunnittelun päämääränä on joko minimoida kokonaislähetysteho tietyllä palvelunlaatuvaatimuksella tai maksimoida pienin saavutettavissa oleva siirtonopeus käyttäjien joukossa tietyllä lähetysteholla. Toisin kuin olemassa olevat menetelmät, ehdotetussa mallissa käytetään yhteisesti sekä aika- että taajuusresursseja usean ryhmän keilanmuodostusta suunniteltaessa. Laajennuksena yhteistoiminnalliselle esikoodaukselle, väitöskirjassa käsitellään myös keilanmuodostusta pilvipohjaisessa radioliityntäverkkoarkkitehtuurissa. Keilanmuodostajat suunnitellaan keskitetysti, kvantisoidaan ja lähetetään datan mukana tukiasemille käyttäen runkoverkkoyhteyttä. Koska käyttäjiä voidaan palvella usealta tukiasemalta, keilanmuodostussuunnittelu muuttuu ei-konveksiksi kombinatoriseksi ongelmaksi. Toisin kuin olemassa olevissa ratkaisuissa, ehdotettu malli sisällyttää käyttäjien datan lisäksi keilanmuodostajien resursoinnin tarpeen runkoverkkoon. Tukiaseman antennien määrän lisääntyessä, keilanmuodostajien osuus runkoverkon käyttöasteesta kasvaa suureksi. Jotta keilanmuodostajien aiheuttamaa ylimääräistä tiedonsiirtotarvetta voitaisiin minimoida, esitellään kaksi tekniikkaa: kvantisointitarkkuuden muunteleminen sekä lähetykseen käytettävien aktiivisten antennien määrän vähentäminen. Lopuksi, jotta yhdistetyn tila-taajuussuunnittelun aiheuttamaa kompleksisuutta saataisiin vähennettyä, ehdotetaan kaksivaiheista menetelmää. MU-MIMO skedulointialgoritmin avulla etsitään ensin alijoukko käyttäjiä jokaiselle skedulointilohkolle. Esikooderit suunnitellaan vain valituille käyttäjille, mikä vähentää kompleksisuutta, heikentämättä suorituskykyä kuitenkaan olennaisesti. Poiketen nolla-avaruuteen perustuvista tekniikoista, esitetään yksinkertainen vektoriprojektioihin perustuva skeduleri. Kaikkien skedulerien reaaliaikasuorituskykyä on arvioitu toteuttamalla ne ohjelmoitavilla Xilinx ZYNQ-ZC702 system-on-chip (SoC) ja TI TCI6636K2H moniydinalustoilla.

This project deals with computation of eigenvalues and eigenvectors of Hermitian positive-semidefinite complex square matrix of order 4. The target is an implementation of computation in language VHDL to field-programmable gate array of type Xilinx Zynq-7000. This master project deals with algorithms used for computation of eigenvalues and eigenvectors of positive-semidefinite symmetric real square and positive-semidefinite complex Hermitian matrix and the analysis of algorithms by AnalyzeAlgorithm program assembled for this purpose. The closing part of this project describes implementation of the computation into field-programmable gate array with use of IP core Xilinx® Floating-Point \linebreak Operator and SVAOptimalizer, SVAInterpreter and SVAToDSPCompiler programs.

FPGAs are of interest in the signal processing domain as they provide the opportunity to run algorithms at very high speed. One possible use case is to sort incoming data in a measurement system, using e.g. a histogram method. Developing code for FPGA applications usually requires knowledge about special languages, which are not common knowledge in the signal processing domain. High-level synthesis is an approach where high-level languages, as MATLAB or C++, can be used together with a code generation tool, to directly generate an FPGA ready output. This thesis uses the development of a histogram as a test case to investigate the efficiency of three different tools, HDL Coder in MATLAB, HDL Coder in Simulink and System Generator for DSP in comparison to the direct development of the same histogram in Vivado using Verilog. How to write and structure code in these tools for proper functionality was also examined. It has been found that all tools deliver an operation frequency comparable to a direct implementation in Verilog, decreased resource usage, a development time which decreased by 27% (HDL Coder in MATLAB), 45% (System Generator) and 64% (HDL Coder in Simulink) but at the cost of increased power consumption. Instructions for how to use all three tools has been collected and summarised. / I ingångssteget på ett mätsystem är det av intresse att använda en FPGA för att uppnå höga hastigheter på de oundvikliga datafiltrering och sorterings algoritmer som körs. Ett problem med FPGAer är att utvecklingen ställer höga krav på specifik kunskap gällande utvecklingsspråk och miljöer vilket för en person specialiserad inom t.ex. signalbehandling kan saknas helt. HLS är en metodik där högnivåspråk kan användas för digital design genom att nyttja ett verktyg för automatgenerering av kod. I detta arbete har utveckling av ett histogram använts som testfall för att utvärdera effektivitet samt designmetodik av tre olika HLS verktyg, HDL Coder till MATLAB, HDL Coder till Simulink och System Generator for DSP. Utvecklingen i dessa verktyg har jämförts mot utvecklingen av samma histogram i Vivado, där språket Verilog använts. Arbetets slutsater är att samtliga verktyg som testats leverar en arbetsfrekvens som är jämförbar med att skriva histogrammet direkt i Verilog, en minskad resursanvändning, utvecklingstid som minskat med 27% (HDL Coder i MATLAB), 45% (System Generator) och 64% (HDL Coder i Simulink) men med en ökad strömförbrukning. En sammanställning av instruktioner för utveckling med hjälp av verktygen har även gjorts.