The primary objective of this thesis is to develop a process for fabricating integrated circuits based on thin-film transistors (TFTs) using zinc tin oxide (ZTO) as the channel layer. ZTO, in contrast to indium- or gallium-based amorphous oxide semiconductors (AOS), is perceived to be a more commercially viable AOS choice due to its low cost and ability to be deposited via DC reactive sputtering. In the absence of an acceptable ZTO wet etch process, a plasma-etching process using Ar/CH₄ is developed for both 1:1 and 2:1 ZTO compositions. An Ar/CH₄ plasma etch process is also designed for indium gallium oxide (IGO), indium gallium zinc oxide (IGZO), and indium tin oxide (ITO). Ar/CH₄ dry etches have excellent selectivity with respect to SiO₂, providing a route for obtaining patterned ZTO channels. A critical asset of ZTO process integration involves removing polymer deposits after ZTO etching without active layer damage. A ZTO process is developed for the fabrication of integrated circuits which use ZTO channel enhancement-mode TFTs. Such ZTO TFTs exhibit incremental and average mobilities of 23 and 18 cm²V⁻¹s⁻¹, respectively, turn-on voltages approximately 0 to 1.5 V and subthreshold swings below 0.5 V/dec when annealed in air at 400 °C for 1 hour. Several types of ZTO TFT circuits are realized for the first time. Despite large parasitic capacitances due to large gate-source and gate-drain overlaps, AC/DC rectifiers are fabricated and found to operate in the MHz range. Thus, they are usable for RFID and other equivalent-speed applications. Finally, a ZTO process for simultaneously fabricating both enhancement-mode and depletion-mode TFTs on a single substrate using a single target and anneal step is developed. This dual-channel process is used to build a high-gain two-transistor enhancement/depletion inverter. At a rail voltage of 10 V, this inverter has a gain of 10.6 V/V, the highest yet reported for an AOS-based inverter. This E/D inverter is an important new functional block which will enable the realization of more complex digital logic circuits. / Graduation date: 2009

Near-field wireless power transfer (WPT) technology facilitates the energy autonomy of heterogeneous systems, significantly augmenting complementary metal-oxide-semiconductor field-effect-transistor (CMOS) technology. In low-power wearable devices, existing power conditioning integrated circuits do not maximize the power factor (PF) for rectification and power conversion efficiency (PCE) due to multiple conversion. Additionally, there is no core power management for the entire power flow. The majority of the research focuses on active rectifiers, which reduce the turn-on voltage for rectification. Certain studies target the output voltage regulation via feedback to the transmitter or direct battery charging without power maximization. Firstly, this study investigates a high-power factor WPT front-end circuit that is namely the mono-periodic switching rectifier (MPSR) and implemented in a 0.18µm 1.8V/5V CMOS process. Integrated phase synchronizers are used to align the waveshape of a wirelessly-coupled sinusoidal voltage source in a receiving coil to the corresponding conducting current. Using this approach, the PF can be increased from roughly 0.6 to unity without requiring any wireless or wired feedback to the transmitter. The proposed MPSR can also provide AC-DC rectification, and step up and down the sinusoidal voltage source's peak amplitude using a pulse-width modulator. Measured voltage conversion ratios range between 0.73X and 2X, and the PF can be boosted up to unity. Secondly, the wireless power system-on-chip (WPower-SoC) is proposed and implemented in a 0.18µm 1.8V/3.3V CMOS process. The WPower-SoC integrating power management can provide rectification, output voltage regulation, and battery charging. Additionally, the implementation of feedforward envelope detection (FED) can reduce the variation in a wireless power link and improve load transient responses. Simulated results demonstrate that 5% of the output voltage regulation is improved when an output load changes. Moreover, the FED reduces approximately 40% of the transient response time. Overshoot and undershoot voltages are decreased by 23% and 26.5%, respectively. The measured output voltage regulates at 3.42V and can supply output power up to 342mW. A temperature sensor as part of the power management core remains active when the WPT receivers enter sleep mode to prolong the battery usage time. In the final part of this study, a nano-watt high-accuracy temperature sensing core is implemented in a 0.18µm 1.8V/3.3V CMOS process that can self-compensate the temperature shift without the need for additional compensating techniques that consume extra power.

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