京都大学 / 0048 / 新制・課程博士 / 博士(理学) / 甲第21441号 / 理博第4434号 / 新制||理||1637(附属図書館) / 京都大学大学院理学研究科物理学・宇宙物理学専攻 / (主査)教授 中家 剛, 教授 鶴 剛, 准教授 市川 温子 / 学位規則第4条第1項該当 / Doctor of Science / Kyoto University / DFAM

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Fourier filtering is a powerful technique to improve the contrast when imaging through turbid media. However, the trade-off between contrast and spatial resolution is a long-standing issue that limits the Fourier filtering technique to low spatial resolution requirements. This report circumvents this trade-off by combining several high contrast but low spatial resolution images into one high spatial resolution, high contrast image using a phase retrieval algorithm. The high contrast, low resolution images were obtained in two methods; rotating an asymmetric Fourier filter and translating a symmetric pinhole filter across the Fourier domain. The former approach, when combined with the phase retrieval algorithm, successfully constructed a high spatial resolution, high contrast image through an optical density of OD = 13.7. The problem with this technique is its temporal sluggishness as several images need to be captured and then processed to form one high resolution image making it difficult to use for fast moving object e.g. Combustion sprays. Here, I propose a new technique called Phase Retrieval Algorithm for Multiple Exposures (PhRAME) which is an instantaneous method to capture all the required images for the phase retrieval algorithm by utilising an ultra-fast imaging technique called Frequency Recognition Algorithm for Multiple Exposures (FRAME). FRAME captures several images in one exposure allowing different spatial frequencies to be captured with the same high contrast in each image. These images are then combined via the phase retrieval algorithm into one high contrast, high spatial resolution image. While this report doesn't demonstrate the working of PhRAME, it demonstrates an intermediately step, that FRAME and the phase retrieval algorithm work in tandem.

Deep neural networks (DNNs) are receiving immense attention because of their ability to solve complex problems. However, running a DNN requires a very large number of computations. Hence, dedicated hardware optimized for running deep learning algorithms known as neuromorphic architectures is often utilized. This dissertation focuses on evaluating andenhancing the accuracy of these neuromorphic architectures considering the designs of components, process variations, and adversarial attacks. The first contribution of the dissertation (Chapter 2) proposes design enhancements in analog Memristive Crossbar Array(MCA)-based neuromorphic architectures to improve classification accuracy. It introduces an analog Winner-Take-All (WTA) architecture and an on-chip training architecture. WTA ensures that the classification of the analog MCA is correct at the final selection level and the highest probability is selected. In particular, this dissertation presents a design of a highly scalable and precise current-mode WTA circuit with digital address generation. The design is based on current mirrors and comparators that use the cross-coupled latch structure. A post-silicon calibration circuit is also presented to handle process variations. On-chip training ensures that there is consistency in classification accuracy among different all analog MCA-based neuromorphic chips. Finally, an enhancement to the analog on-chip training architecture by implementing the Convolutional Neural Network (CNN) on MCA and software considerations to accelerate the training is presented.The second focus of the dissertation (Chapter 3) is on producing correct classification in the presence of malicious inputs known as adversarial attacks. This dissertation shows that MCA-based neuromorphic architectures ensure correct classification when the input is compromised using existing adversarial attack models. Furthermore, it shows that adversarialrobustness can be further improved by compression-based preprocessing steps that can be implemented on MCAs. It also evaluates the impact of the architecture in Chapter 2 under adversarial attacks. It shows that adversarial attacks do not uniformly affect the classification accuracy of different MCA-based chips. Experimental evidence using a variety of datasets and attack models supports the impact of MCA-based neuromorphic architectures and compression-based preprocessing implemented on MCAs to mitigate adversarial attacks. It is also experimentally shown that the on-chip training improves consistency in mitigating adversarial attacks among different chips. The final contribution (Chapter 4) of this dissertation introduces an enhancement of the method in Chapter 3. It consists of input preprocessing using compression and subsequent rescale and rearrange operations that are implemented using MCAs. This approach further improves the robustness against adversarial attacks. The rescale and rearrange operations are implemented using a DNN consisting of fully connected and convolutional layers. Experimental results show improved defense compared to similar input preprocessing techniques on MCAs.

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Today's large-scale, high-performance, data-intensive applications put a tremendous stress on data centers to store, index, and retrieve large amounts of data. Exemplified by technologies such as social media, photo and video sharing, and e-commerce, the rise of the real-time web demands data stores support minimal latencies, always-on availability and ever-growing capacity. These requirements have fostered the development of a large number of high-performance storage systems, arguably the most important of which are Key-Value (KV) stores. An emerging trend for achieving low latency and high throughput in this space is a solution, which utilizes both DRAM and flash by storing an efficient index for the data in memory and minimizing accesses to flash, where both keys and values are stored. Many proposals have examined how to improve KV store performance in this area. However, these systems have shortcomings, including expensive sorting and excessive read and write amplification, which is detrimental to the life of the flash. Another trend in recent years equips large scale deployments with energy-efficient, high performance co-processors, such as Graphics Processing Units (GPUs). Recent work has explored using GPUs to accelerate compute-intensive I/O workloads, including RAID parity generation, encryption, and compression. While this research has proven the viability of GPUs to accelerate these workloads, we argue that there are significant benefits to be had by developing methods and data structures for deep integration of GPUs inside the storage stack, in order to achieve better performance, scalability, and reliability. In this dissertation, we propose comprehensive frameworks that leverage emerging technologies, such as GPUs and flash-based SSDs, to accelerate modern storage systems. For our accelerator-based solution, we focus on developing a system that features deep integration of the GPU in a distributed parallel file system. We utilize a framework that builds on the resources available in the file system and coordinates the workload in such a way that minimizes data movement across the PCIe bus, while exposing data parallelism to maximize the potential for acceleration on the GPU. Our research aims to improve the overall reliability of a PFS by developing a distributed per-file parity generation that provides end-to-end data integrity and unprecedented flexibility. Finally, we design a high-performance KV store utilizing a novel data structure tailored to specific flash requirements; it arranges data on flash in such a way as to minimize write amplification, which is detrimental to the flash cells. The system delivers outstanding read amplification through the use of a trie index and false positive filter. / Ph. D.

The quick growth of embedded systems and their increasing computing power has made them suitable for a wider range of applications. Despite the increasing performance of modern embedded processors, they are outpaced by computational demands of the growing number of modern applications. This trend has led to emergence of hardware accelerators in embedded systems. While the processing power of dedicated hardware modules seems appealing, they require significant effort of development and integration to gain performance benefit. Thus, it is prudent to investigate and estimate the integration overhead and consequently the hardware acceleration benefit before committing to implementation. In this work, we present FPGA-Roofline, a visual model that offers insights to designers and developers to have realistic expectations of their system and that enables them to do their design and analysis in a faster and more efficient fashion. FPGA-Roofline allows simultaneous analysis of communication and computation resources in FPGA-based hardware accelerators. To demonstrate the effectiveness of our model, we have implemented hardware accelerators in FPGA and used our model to analyze and optimize the overall system performance. We show how the same methodology can be applied to the design process of any FPGA-based hardware accelerator to increase productivity and give insights to improve performance and resource utilization by finding the optimal operating point of the system. / Master of Science

Sweden has proven to be a fruitful country when it comes to history and ancient archeological monuments. However one specific type of ancient monument stands out in both quantity and in their distribution, trappings pits. Sweden has about 30 000 documented trapping pits spread throughout northern Sweden. However, even though there is a large quantity of trapping pits that have been documented, determining the age of a trapping pit is a difficult task. This practice has been largely debated by Swedish archaeologists and is to this day seen as problematic when it comes to the radiocarbon dating of trapping pits. This thesis will discuss these topics. What exactly does the date show? Will it show the time of its construction? Perhaps the time of its use? Or it could be completely erroneous? Receiving a false radiocarbon dating of an ancient monument could prove very controversial and adverse, because reliable dates are the very foundation needed in order to place an ancient monument in a context. Without being able to date an ancient monument, interpretations of societal origin and function will be harder to determine and largely up for debate. Chronologies only reflect and represent the data and information that has been fed into it. This often leaves an uncertainty concerning which data that actually shows an open and honest representation of trapping pits, and which data shows a false or misleading representation. This thesis will therefore analyze previous chronologies that have been used to represent trapping pits and show exactly how the data was gathered, used and represented. Three primary archaeological studies will therefore be showcased and analyzed to determine if the result can actually represent an honest timeframe of when the pits were constructed.

The initial goal of the project as given to us was a fully automatic control system for the beam align-ment of an ion microprobe in order to improve efficiency building on previous automation efforts.We have worked in python to develop code for reading two 4-channel picoammeters connected toadjustable rods along the beam line and translating those electrical readings into a calculated beamposition with no visual input. We then use this to recommend current adjustments to the steeringdipole electromagnets. Development was started on a standalone GUI to ease this process for newbeam compositions but was not feature complete in time.

The thesis presents phase stability studies for the Compact Linear Collider (CLIC) and focuses in particular on CLIC Drive Beam longitudinal phase stabilisation. This topic constitutes one of the main feasibility challenges for CLIC construction and is an essential component of the current CLIC stabilisation campaign. The studies are divided into two large interrelated sections: the simulation studies for the CLIC Drive Beam stability, and measurements, data analysis and simulations of the CLIC Test Facility (CTF3) Drive Beam phase errors. A dedicated software tool has been developed for a step-by-step analysis of the error propagation through the CLIC Drive Beam. It uses realistic RF potential and beam loading amplitude functions for the Drive and Main Beam accelerating structures, complete models of the recombination scheme and compressor chicane as well as of further CLIC Drive Beam modules. The tool has been tested extensively and its functionality has been verified. The phase error propagation at CLIC has been analysed and the critical phase error frequencies have been identified. The impact of planned error filtering and stabilisation systems for the Drive Beam bunch charge and longitudinal phase has been simulated and the optimal specifications for these systems, such as bandwidth and latency time, have been calculated and discussed. It has been found that a realistic feed-forward system could sufficiently reduce the longitudinal phase error of the Drive Beam, hence verifying that a satisfactory CLIC luminosity recovery system is possible to develop. Alternative designs of the Drive Beam accelerator, the recombination scheme and the phase signal distribution system have also been analysed. Measurements of the CTF3 Drive Beam phase have been performed. The source of the phase and energy errors at CTF3 has been determined. The performance of the phase feed-forward system prototype for CTF3 has been simulated. The prototype's specifications have been defined so that it will provide a sufficient test of the feed-forward correction principle. The prototype based on the defined specifications is currently in development and is to be installed at CTF3 in the second half of 2013.