This paper is the use of the active inductor instead of passive inductors to save area, enter the match aspects of the use of the feedback capacitor in parallel with the resistor to achieve matching with the control input voltage, in addition to adjusting the feedback resistor can control the noise. The LNA dissipates 13.2 mW power and achieves input return loss (S11) below -10dB, output return loss (S22) below -10 dB, forward gain (S21) of 11.3~14.5dB, reverse isolation (S12) below -40dB, and noise figure (NF) of 3~3.18 dB. 1-dB compression point (P1dB) of -24 dBm and input third-order inter-modulation point (IIP3) of -14 dBm .

This thesis explores the use of active inductors as a compact alternative to the bulky passive spiral structures in high-speed I/O circuits. A newly proposed PMOS-based topology is introduced and used in active-inductor terminations. The 1st prototype design fabricated in a 90-nm CMOS process consists of an output driver using active-inductor terminations to provide channel equalization and output impedance matching. From measurement results, the use of active inductors in the termination, as compared to when the active inductor is disabled, increases the vertical eye opening in the receiver side by a factor of two and reduces the jitterp-p by 30% of the transmitted 10 Gb/s (2³¹-1) pseudo-random binary sequence pattern, over a 6-inch FR4 channel. An output impedance matching with S₂₂ less than -10 dB over a bandwidth of 20 GHz is achieved. The pair of active-inductor terminations occupies 17×25 µm² and has a low overhead power consumption of 0.8 mW. In the 2nd prototype design, a 4-stage output buffer with active-inductor loads is designed and implemented in a 65-nm CMOS process. Simulation results verify that when operating at 31.25 Gb/s, the output eye of the active-inductor load buffer compares favorably with that of the passive-inductor load buffer. For a similar eye-height and 78% less timing jitter the active-inductor load design’s speed (31.25 Gb/s) is 25% faster than the passive-resistor load design (25 Gb/s). The active-inductor load output buffer achieves comparable performance in terms of speed, power, and output swing with other reported designs using passive inductors. Its total area is 135×30 µm² (including three differential active inductors) which is comparable to the size of a single passive spiral inductor having a 0.5~1 nH inductance.

This thesis explores the use of active inductors as a compact alternative to the bulky passive spiral structures in high-speed I/O circuits. A newly proposed PMOS-based topology is introduced and used in active-inductor terminations. The 1st prototype design fabricated in a 90-nm CMOS process consists of an output driver using active-inductor terminations to provide channel equalization and output impedance matching. From measurement results, the use of active inductors in the termination, as compared to when the active inductor is disabled, increases the vertical eye opening in the receiver side by a factor of two and reduces the jitterp-p by 30% of the transmitted 10 Gb/s (2³¹-1) pseudo-random binary sequence pattern, over a 6-inch FR4 channel. An output impedance matching with S₂₂ less than -10 dB over a bandwidth of 20 GHz is achieved. The pair of active-inductor terminations occupies 17×25 µm² and has a low overhead power consumption of 0.8 mW. In the 2nd prototype design, a 4-stage output buffer with active-inductor loads is designed and implemented in a 65-nm CMOS process. Simulation results verify that when operating at 31.25 Gb/s, the output eye of the active-inductor load buffer compares favorably with that of the passive-inductor load buffer. For a similar eye-height and 78% less timing jitter the active-inductor load design’s speed (31.25 Gb/s) is 25% faster than the passive-resistor load design (25 Gb/s). The active-inductor load output buffer achieves comparable performance in terms of speed, power, and output swing with other reported designs using passive inductors. Its total area is 135×30 µm² (including three differential active inductors) which is comparable to the size of a single passive spiral inductor having a 0.5~1 nH inductance.

This thesis explores the use of active inductors as a compact alternative to the bulky passive spiral structures in high-speed I/O circuits. A newly proposed PMOS-based topology is introduced and used in active-inductor terminations. The 1st prototype design fabricated in a 90-nm CMOS process consists of an output driver using active-inductor terminations to provide channel equalization and output impedance matching. From measurement results, the use of active inductors in the termination, as compared to when the active inductor is disabled, increases the vertical eye opening in the receiver side by a factor of two and reduces the jitterp-p by 30% of the transmitted 10 Gb/s (2³¹-1) pseudo-random binary sequence pattern, over a 6-inch FR4 channel. An output impedance matching with S₂₂ less than -10 dB over a bandwidth of 20 GHz is achieved. The pair of active-inductor terminations occupies 17×25 µm² and has a low overhead power consumption of 0.8 mW. In the 2nd prototype design, a 4-stage output buffer with active-inductor loads is designed and implemented in a 65-nm CMOS process. Simulation results verify that when operating at 31.25 Gb/s, the output eye of the active-inductor load buffer compares favorably with that of the passive-inductor load buffer. For a similar eye-height and 78% less timing jitter the active-inductor load design’s speed (31.25 Gb/s) is 25% faster than the passive-resistor load design (25 Gb/s). The active-inductor load output buffer achieves comparable performance in terms of speed, power, and output swing with other reported designs using passive inductors. Its total area is 135×30 µm² (including three differential active inductors) which is comparable to the size of a single passive spiral inductor having a 0.5~1 nH inductance. / Applied Science, Faculty of / Electrical and Computer Engineering, Department of / Graduate

Indutores Ativos são circuitos que quando utilizados se mostram como uma opção viável para melhorar o aproveitamento de área do chip e o fator de qualidade do indutor, comparado com indutor passivo, além de possibilitar o ajuste de parâmetros. Neste trabalho foram estudadas três topologias e abordagens encontradas na literatura para indutores ativos: indutor ativo simples, indutor ativo cascode, indutor ativo com resistência de realimentação. Propomos uma técnica para garantir que o indutor ativo não apresente pólos com parte real positiva, quando conectado a um circuito RC externo, através do cancelamento entre um pólo e um zero. Propomos também uma nova abordagem de projeto para a topologia indutor ativo com resistência de realimentação a qual chamamos de indutor ativo com baixa resistência de realimentação. Para estudo de aplicabilidade foi projetado um LNA (Low Noise Amplifier) utilizando a abordagem de projeto proposta. O amplificador deve atender requisitos de ganho, frequência de operação, impedância de entrada, consumo de potência, figura de ruído além de estabilidade para cargas de saída (pólos com parte real sempre positiva), utilizando o indutor ativo com baixa resistência de realimentação. / Active inductors are circuits that when used prove to be a viable option to improve chip area usage and the inductor\'s quality factor, compared to the passive inductor, while also allowing parameter adjustment. This work studies three topologies and approaches found in literature for active inductors: simple active inductor, cascode active inductor, active inductor with feedback resistance. We propose a technique to guarantee that the active inductor doesn\'t present poles with a positive real part, when connected to an external RC circuit, through cancelling between a pole and a zero. We also propose a new project approach for the topology of the active inductor with feedback resistance which we call low feedback resistance active inductor. To assess the applicability, a LNA (Low Noise Amplifier) was projected using the proposed project approach. The amplifier must meet the requirements regarding gain, operation frequency, input impedance, power consumption, noise figure and also stability for output loads (poles with an always negative real part), using the low feedback resistance active inductor.

A crescente necessidade de produzir circuitos integrados (CIs) cada vez mais miniaturizados para aplicações na faixa de microondas (frequências acima de 1 GHz) com baixo custo de produção e baixo consumo de potênca tem motivado a utilização da tradicional tecnologia Complementary Metal Oxide Semiconductor (CMOS) sobre substrato de silício (Si). Uma aplicação de particular interesse em circuitos integrados operando na faixa de microondas a dos indutores ativos. Rotineiramente, estes indutores ativos são fabricados por meio de processos relativamente custosos como aqueles normalmente envolvidos em tecnologias empregando substrato de arsenato de gálio (GaAs). Por outro lado, novas técnicas de litografia CMOS têm possibilitado a construção de transientes MOSFETs alcançando elevadas frequências de operação. Dessa maneira, o objetivo principal deste trabalho é realizar uma investigação da possibilidade de implementação de indutores ativos operando na faixa de microondas empregando uma tecnologia CMOS convencional sobre substrato de silício. Historicamente, a tecnologia CMOS é atrativa devido às suas características de baixo custo de produção, baixo consumo de potência, alta imunidade aos ruídos e também por oferecer maturidade tecnológica. / The growing need to produce integrated circuits (ICs) increasingly miniaturized for applications in the microwave range (frequencies above 1 GHz) with low cost of production and low consumption power has been stimulating the utilization of traditional technology complementary metal oxide semiconductor (CMOS) on silicon (Si) substrate. One application of particular interest in integrated circuits operating in the microwave range is the active inductors. Ordinarily, these active inductors are fabricated by using relatively expensive technological processes like those usually involved in the gallium arsenide (GaAs) technology. Nonetheless, new techniques of lithography applied to CMOS technology have allowed fabricating MOSFETs transistors reaching high frequencies of operation. In this way, the main goal of this work is realize an investigation of the possibility to implement active inductors operating in the microwave range by using traditional CMOS technology, developed on silicon substrate. Historically, the CMOS technology is attractive by its characteristics of low cost of production, low consumption of power, high immunity to noise and also by offering technological maturity.

Inter-chip input-output (I/O) communication bandwidth demand, which rapidly scaled with integrated circuit scaling, requires high performance I/O links to achieve a per pin data rate as high as multi-Gb/s. The design of high-speed links employing forwarded-clock architecture enables jitter tracking between data and clock from low to high frequencies. Considering the impact of clock to data skew, high frequency sampling clock jitter and data jitter become out of phase at receiver, which reduces the timing margin and limits the data rate. The jitter tracking bandwidth (JTB) between data and clock should be optimized to compensate the clock to data skew. System level analysis shows that the wide tunable range of JTB is needed to compensate different amounts of skews. The implementation of bandpass filtering on forwarded-clock path is able to control the JTB through the controlling of Q. This work introduces a method using bandpass filtering to optimize the JTB in high-speed forwarded-clock transceivers, followed by the implementation of active-inductor-based bandpass filter as clock receiver, which has advantages of low-voltage operation, low power as well as low area consumption. Simulation results shows that the designed filter provides controllable JTB over 40 - 600MHz. The bandpass filter is implemented in IBM 90nm CMOS process.

No description available.

A crescente necessidade de produzir circuitos integrados (CIs) cada vez mais miniaturizados para aplicações na faixa de microondas (frequências acima de 1 GHz) com baixo custo de produção e baixo consumo de potênca tem motivado a utilização da tradicional tecnologia Complementary Metal Oxide Semiconductor (CMOS) sobre substrato de silício (Si). Uma aplicação de particular interesse em circuitos integrados operando na faixa de microondas a dos indutores ativos. Rotineiramente, estes indutores ativos são fabricados por meio de processos relativamente custosos como aqueles normalmente envolvidos em tecnologias empregando substrato de arsenato de gálio (GaAs). Por outro lado, novas técnicas de litografia CMOS têm possibilitado a construção de transientes MOSFETs alcançando elevadas frequências de operação. Dessa maneira, o objetivo principal deste trabalho é realizar uma investigação da possibilidade de implementação de indutores ativos operando na faixa de microondas empregando uma tecnologia CMOS convencional sobre substrato de silício. Historicamente, a tecnologia CMOS é atrativa devido às suas características de baixo custo de produção, baixo consumo de potência, alta imunidade aos ruídos e também por oferecer maturidade tecnológica. / The growing need to produce integrated circuits (ICs) increasingly miniaturized for applications in the microwave range (frequencies above 1 GHz) with low cost of production and low consumption power has been stimulating the utilization of traditional technology complementary metal oxide semiconductor (CMOS) on silicon (Si) substrate. One application of particular interest in integrated circuits operating in the microwave range is the active inductors. Ordinarily, these active inductors are fabricated by using relatively expensive technological processes like those usually involved in the gallium arsenide (GaAs) technology. Nonetheless, new techniques of lithography applied to CMOS technology have allowed fabricating MOSFETs transistors reaching high frequencies of operation. In this way, the main goal of this work is realize an investigation of the possibility to implement active inductors operating in the microwave range by using traditional CMOS technology, developed on silicon substrate. Historically, the CMOS technology is attractive by its characteristics of low cost of production, low consumption of power, high immunity to noise and also by offering technological maturity.

Indutores Ativos são circuitos que quando utilizados se mostram como uma opção viável para melhorar o aproveitamento de área do chip e o fator de qualidade do indutor, comparado com indutor passivo, além de possibilitar o ajuste de parâmetros. Neste trabalho foram estudadas três topologias e abordagens encontradas na literatura para indutores ativos: indutor ativo simples, indutor ativo cascode, indutor ativo com resistência de realimentação. Propomos uma técnica para garantir que o indutor ativo não apresente pólos com parte real positiva, quando conectado a um circuito RC externo, através do cancelamento entre um pólo e um zero. Propomos também uma nova abordagem de projeto para a topologia indutor ativo com resistência de realimentação a qual chamamos de indutor ativo com baixa resistência de realimentação. Para estudo de aplicabilidade foi projetado um LNA (Low Noise Amplifier) utilizando a abordagem de projeto proposta. O amplificador deve atender requisitos de ganho, frequência de operação, impedância de entrada, consumo de potência, figura de ruído além de estabilidade para cargas de saída (pólos com parte real sempre positiva), utilizando o indutor ativo com baixa resistência de realimentação. / Active inductors are circuits that when used prove to be a viable option to improve chip area usage and the inductor\'s quality factor, compared to the passive inductor, while also allowing parameter adjustment. This work studies three topologies and approaches found in literature for active inductors: simple active inductor, cascode active inductor, active inductor with feedback resistance. We propose a technique to guarantee that the active inductor doesn\'t present poles with a positive real part, when connected to an external RC circuit, through cancelling between a pole and a zero. We also propose a new project approach for the topology of the active inductor with feedback resistance which we call low feedback resistance active inductor. To assess the applicability, a LNA (Low Noise Amplifier) was projected using the proposed project approach. The amplifier must meet the requirements regarding gain, operation frequency, input impedance, power consumption, noise figure and also stability for output loads (poles with an always negative real part), using the low feedback resistance active inductor.