This thesis proposed solutions to some shortcomings to current eLearning architectures. The proposed DeLC architecture supports context-aware and adaptable provision of eLearning services and electronic content. The architecture is fully distributed and integrates service-oriented development with agent technology. Central to this architecture is that a node is our unit of computation (known as eLearning node) which can have purely service-oriented architecture, agent-oriented architecture or mixed architecture. Three eLeaerning Nodes have been implemented in order to demonstrate the vitality of the DeLC concept. The Mobile eLearning Node uses a three-level communication network, called InfoStations network, supporting mobile service provision. The services, displayed on this node, are to be aware of its context, gather required learning material and adapted to the learner request. This is supported trough a multi-layered hybrid (service- and agent-oriented) architecture whose kernel is implemented as middleware. For testing of the middleware a simulation environment has been developed. In addition, the DeLC development approach is proposed. The second eLearning node has been implemented as Education Portal. The architecture of this node is poorly service-oriented and it adopts a client-server architecture. In the education portal, there are incorporated education services and system services, called engines. The electronic content is kept in Digital Libraries. Furthermore, in order to facilitate content creators in DeLC, the environment Selbo2 was developed. The environment allows for creating new content, editing available content, as well as generating educational units out of preexisting standardized elements. In the last two years, the portal is used in actual education at the Faculty of Mathematics and Informatics, University of Plovdiv. The third eLearning node, known as Agent Village, exhibits a purely agent-oriented architecture. The purpose of this node is to provide intelligent assistance to the services deployed on the Education Pportal. Currently, two kinds of assistants are implemented in the node - eTesting Assistants and Refactoring eLearning Environment (ReLE). A more complex architecture, known as Education Cluster, is presented in this thesis as well. The Education Cluster incorporates two eLearning nodes, namely the Education Portal and the Agent Village. eLearning services and intelligent agents interact in the cluster.

Many digital logic applications can take advantage of the reconfiguration capability of Field Programmable Gate Arrays (FPGAs) to dynamically patch design flaws, recover from faults, or time-multiplex between functions. Partial reconfiguration is the process by which a user modifies one or more modules residing on the FPGA device independently of the others. Partial Reconfiguration reduces the granularity of reconfiguration to be a set of columns or rectangular region of the device. Decreasing the granularity of reconfiguration results in reduced configuration filesizes and, thus, reduced configuration times. When compared to one bitstream of a non-partial reconfiguration implementation, smaller modules resulting in smaller bitstream filesizes allow an FPGA to implement many more hardware configurations with greater speed under similar storage requirements. To realize the benefits of partial reconfiguration in a wider range of applications, this thesis begins with a survey of FPGA fault-handling methods, which are compared using performance-based metrics. Performance analysis of the Genetic Algorithm (GA) Offline Recovery method is investigated and candidate solutions provided by the GA are partitioned by age to improve its efficiency. Parameters of this aging technique are optimized to increase the occurrence rate of complete repairs. Continuing the discussion of partial reconfiguration, the thesis develops a case-study application that implements one partial reconfiguration module to demonstrate the functionality and benefits of time multiplexing and reveal the improved efficiencies of the latest large-capacity FPGA architectures. The number of active partial reconfiguration modules implemented on a single FPGA device is increased from one to eight to implement a dynamic video-processing architecture for Discrete Cosine Transform and Motion Estimation functions to demonstrate a 55-fold reduction in bitstream storage requirements thus improving partial reconfiguration capability.

The design of a common architecture that can support multiple data-flow patterns (or contexts) embedded in complex control flow structures, in applications like multimedia processing, is particularly challenging when the target platform is a Field Programmable Gate Array (FPGA) with a heterogeneous mixture of device primitives. This thesis presents scheduling and mapping algorithms that use a novel area cost metric to generate resource aware context adaptable architectures. Results of a rigorous analysis of the methodology on multiple test cases are presented. Results are compared against published techniques and show an area savings and execution time savings of 46% each.