VLSI circuits in nanometer VLSI technology experience significant variations - intrinsic process variations and variations brought about by transistor degradation or aging. These are generally embodied by yield loss or performance degradation over operation time. Although the degradation can be compensated by the worst-case scenario based over-design approach, it induces remarkable power overhead which is undesirable in tightly power-constrained designs. Dynamic voltage scaling (DVS) is a more powerefficient approach. However, its coarse granularity implies difficulty in handling finegrained variations. These factors have contributed to the growing interest in poweraware robust circuit design. In this thesis, we propose a Built-In Proactive Tuning (BIPT) system, a lowpower typical case design methodology based on dynamic prediction and prevention of possible circuit timing errors. BIPT makes use of the canary circuit to predict the variation induced performance degradation. The approach presented allows each circuit block to autonomously tune its performance according to its own degree of variation. The tuning is conducted offline, either at power on or periodically. A test pattern generator is included to reduce the uncertainty of the aging prediction due to different input vectors. The BIPT system is validated through SPICE simulations on benchmark circuits with consideration of process variations and NBTI, a static stress based PMOS aging effect. The experimental results indicate that to achieve the same variation resilience, proposed BIPT system leads to 33% power savings in case of process variations as compared to the over-design approach. In the case of aging resilience, the approach proposed in this thesis leads to 40% less power than the approach of over-design while 30% less power as compared to DVS with NBTI effect modeling.

Variability affects the performance and power of a circuit. Along with static variations, dynamic variations, which occur during chip operation, necessitate a safety margin. The safety margin makes it difficult to meet the target performance within a limited power budget. This research explores methodologies to minimize the safety margin, thereby improving the energy efficiency of a system. The safety margin can be reduced by either minimizing the variation or adapting to the variation. This research explores three different methods to compensate for variations efficiently. First, post-silicon tuning methods for minimizing variations in 3D ICs are presented. Design methodologies to apply adaptive voltage scaling and adaptive body biasing to 3D ICs and the associated circuit techniques are explored. Second, non-design-intrusive circuit techniques are proposed for adaptation to dynamic variations. This work includes adaptive clock modulation and bias-voltage generation techniques. Third, design-intrusive methods to eliminate the safety margin are proposed. The proposed methodologies can prevent timing-errors in advance with a minimized performance penalty. As a result, the methods presented in this thesis minimize static variations and adapt to dynamic variations, thereby, enabling robust low-power operation of digital systems.

In many digital designs there is a need to use multi-stage tapered buffers to drive large capacitive loads. These buffers contribute a significant percentage of overall power. In this thesis, we propose two novel tunable buffer designs that enable reduction in power in the presence of process variation. A strategy to derive the optimal buffer size and the optimal tuning rule in post-silicon phase is developed. By comparing several tunable buffer circuit topologies, we also demonstrate the tradeoffs in tunable buffer topology selection as a function of switching activity, timing requirements, and the magnitude of process variations. Using HSPICE simulations based on the high performance 32nm ASU Predictive Model, we show that up to 30% average power reduction can be achieved for a SRAM word-line decoder while maintaining the same timing yield. / text