Thesis (Ph.D.)--Drexel University, 2009. / Includes abstract and vita. Includes bibliographical references (leaves 198-210).

Thesis (M.S.)--Ohio University, June, 2004. / Includes bibliographical references (p. 67-70).

Thesis (M.S. in Electrical Engineering)--Naval Postgraduate School, March 2005. / Thesis Advisor(s): Douglas J. Fouts. Includes bibliographical references (p. 103-105). Also available online.

Thesis (M.S.)--Ohio University, June, 2004. / Title from PDF t.p. Includes bibliographical references (p. 67-70)

Approved for public release; distribution is unlimited / Communication is an essential skill for every military officer. Their jobs are accomplished through communication This thesis evaluates the usefulness of the SRC-6E reconfigurable computing system for a radar signal processing application and documents the process of creating and importing VHDL code to configure the user definable logic on the SRC-6E. The research builds on previous work which implemented a false radar imaging algorithm on the SRC-6E. Data from alternative computational approaches to the same problem are compared to determine the effectiveness of SRC-6E solution. The results show that the SRC-6E provides and effective solution for implementations with greater than 64 range bins. An evaluation of the SRC-6E difficulty of use is conducted, including a discussion of required skills, experience and development times. The algorithm test code is included in the appendices.

With the rise of mobile computing and an ever-growing variety of ubiquitous sensors, computers are becoming increasingly context-aware. A revolutionary step in this process that has seen much progress will be user-awareness: the ability of a computing device to infer its user's emotions. This research project attempts to study the effectiveness of enabling a computer to adapt its visual interface to counter user frustration. A two-group experiment was designed to engage participants in a goal-oriented task disguised as a simple usability study with a performance incentive. Five frustrating stimuli were triggered throughout a single 15-minute task in the form of complete system unresponsiveness or delay. An algorithm was implemented to attempt to detect sudden rises in user arousal measured via a skin conductance sensor. Following a successful detection, or otherwise a maximum of a 10-second delay, the application resumed responsiveness. In the control condition, participants were exposed to a “please wait” pop-up near the end of the delay whereas those in the adaption condition were exposed to an additional visual transition to a user interface with calming colours and larger touch targets. This proposed adaptive condition was hypothesized to reduce the recovery time associated with the frustration response. The experiment was successfully able to induce frustration (via measurable skin conductance responses) in the majority of trials. The mean recovery half-time of participants in the first trial adaptive condition was significantly longer than that of the control. This was attributed to a possibility of a large chromatic difference between the adaptive and control colour schemes, habituation and prediction, causal association of adaptation to the frustrating stimulus, as well as insufficient subtlety in the transition and visual look of the adaptive interface. The study produced findings and guidelines that will be crucial in the future design of adaptive affective user interfaces.

Thesis (M.S. in Computer Science)--Naval Postgraduate School, June 2004. / Thesis advisor(s): Neil Rowe. Includes bibliographical references (p. 129-130). Also available online.

Thesis (M.S. in Electrical Engineering)--Naval Postgraduate School, December 2003. / Thesis advisor(s): Douglas Fouts, Ted Lewis. Includes bibliographical references (p. 125). Also available online.

With the rise of mobile computing and an ever-growing variety of ubiquitous sensors, computers are becoming increasingly context-aware. A revolutionary step in this process that has seen much progress will be user-awareness: the ability of a computing device to infer its user's emotions. This research project attempts to study the effectiveness of enabling a computer to adapt its visual interface to counter user frustration. A two-group experiment was designed to engage participants in a goal-oriented task disguised as a simple usability study with a performance incentive. Five frustrating stimuli were triggered throughout a single 15-minute task in the form of complete system unresponsiveness or delay. An algorithm was implemented to attempt to detect sudden rises in user arousal measured via a skin conductance sensor. Following a successful detection, or otherwise a maximum of a 10-second delay, the application resumed responsiveness. In the control condition, participants were exposed to a “please wait” pop-up near the end of the delay whereas those in the adaption condition were exposed to an additional visual transition to a user interface with calming colours and larger touch targets. This proposed adaptive condition was hypothesized to reduce the recovery time associated with the frustration response. The experiment was successfully able to induce frustration (via measurable skin conductance responses) in the majority of trials. The mean recovery half-time of participants in the first trial adaptive condition was significantly longer than that of the control. This was attributed to a possibility of a large chromatic difference between the adaptive and control colour schemes, habituation and prediction, causal association of adaptation to the frustrating stimulus, as well as insufficient subtlety in the transition and visual look of the adaptive interface. The study produced findings and guidelines that will be crucial in the future design of adaptive affective user interfaces.

In the past two decades, FPGA has been witnessed from its restricted use as glue logic towards real System-on-Chip (SoC) platforms. Profiting from the great development on semiconductor and IC technologies, the programmability of FPGAs enables themselves wide adoption in all kinds of aspects of embedded designs. Modern FPGAs provide the additional capability of being dynamically and partially reconfigured during the system run-time. The run-time reconfigurability enhances FPGA designs from the sole spatial to both spatial and temporal parallelism, providing more design flexibility for advanced system features. Adaptive computing delegates an advanced computing paradigm in which computation tasks and resources are intelligently managed in correspondence with conditional requirements. In this thesis, we investigate adaptive designs on FPGA platforms: We present a comprehensive and practical design framework for adaptive computing based on the FPGA run-time reconfigurability. It concerns several design key issues in different hardware/software layers, specifically hardware architecture, run-time reconfiguration technical support, OS and device drivers, hardware process scheduler, context switching as well as Inter-Process Communications (IPC). Targeting a special application of data acquisition (DAQ) and trigger systems in nuclear and particle physics experiments, we set up the data streaming model and conduct theoretical analysis on the adaptive system. Three application studies are employed to verify the proposed adaptive design framework: The first application demonstrates a peripheral controller adaptable system aiming at general embedded designs. Through dynamically loading/unloading a NOR flash memory controller and an SRAM controller, both flash memory and SRAM accesses may be accomplished with less resource consumption than in traditional static designs. In the second case, two real algorithm processing engines are adaptively time-multiplexed in the same reconfigurable slot for particle recognition computation. Experimental results reveal the reduced on-chip resource requirements, as well as an approximate processing capability of the peer static design. Taking advantage of the FPGA dynamic reconfigurability, we present in the third application a novel on-FPGA interconnection microarchitecture named RouterLess NoC (RL-NoC). RL-NoC employs the novel design concept of Move Logic Not Data (MLND), and significantly distinguishes itself from the existing interconnection architectures such as buses, crossbars or NoCs. It does not rely on routers to deliver packets hop by hop as canonical NoCs do, but buffers data packets in virtual channels and brings various nodes using run-time reconfiguration to produce or consume them. In comparison with canonical packet-switching NoCs, the routerless architecture features lower design complexity, less resource consumption, higher work frequency, more efficient power dissipation as well as comparable or even higher packet delivery efficiency. It is regarded as a promising interconnection approach in some design scenarios on FPGAs, especially for light-weight applications. / QC 20110531