<p>This thesis is a part of a bigger project which goal is to make a DSP that is instruction compatible with the Motorola DSP56002. The goal of this part is to make a behavioural model with timing of the address generation unit in the DSP. </p><p>The AGU unit can handle 4 different types of arithmetic’s including linear addressing, modulo addressing, wrap around modulo addressing and reverse carry addressing. It also handles several ways of calculating addresses as post/pre increment/decrement by a number. It can address 3 different memories, where 2 new addresses can be calculated at the same time in different memories. </p><p>This model will be used as a golden model for the RTL model of the AGU that is one of the main parts in the DSP.</p>

This thesis is a part of a bigger project which goal is to make a DSP that is instruction compatible with the Motorola DSP56002. The goal of this part is to make a behavioural model with timing of the address generation unit in the DSP. The AGU unit can handle 4 different types of arithmetic’s including linear addressing, modulo addressing, wrap around modulo addressing and reverse carry addressing. It also handles several ways of calculating addresses as post/pre increment/decrement by a number. It can address 3 different memories, where 2 new addresses can be calculated at the same time in different memories. This model will be used as a golden model for the RTL model of the AGU that is one of the main parts in the DSP.