Submitted by Renata Lopes (renatasil82@gmail.com) on 2017-04-20T17:56:56Z No. of bitstreams: 1 luisguilhermedasilvacosta.pdf: 5093972 bytes, checksum: 6380895e21a76520d3f4a10aad5a3371 (MD5) / Approved for entry into archive by Adriana Oliveira (adriana.oliveira@ufjf.edu.br) on 2017-04-24T16:50:02Z (GMT) No. of bitstreams: 1 luisguilhermedasilvacosta.pdf: 5093972 bytes, checksum: 6380895e21a76520d3f4a10aad5a3371 (MD5) / Made available in DSpace on 2017-04-24T16:50:02Z (GMT). No. of bitstreams: 1 luisguilhermedasilvacosta.pdf: 5093972 bytes, checksum: 6380895e21a76520d3f4a10aad5a3371 (MD5) Previous issue date: 2012-02-24 / Atualmente, há um grande interesse no desenvolvimento de transceptores PLC (power line communication) para a transmissão banda larga e banda estreita de dados visando, sobretudo, aplicações smart grids e de acesso banda larga. Para o avanço da tecnologia PLC, há grande demanda pela introdução de acopladores com características e desempenhos que viabilizem a conexão dos tranceptores PLC `as redes de energia elétrica, com o mínimo de distorção possível. Neste contexto, a presente contribuição versa sobre o estudo, a investigação, especificação, projeto e análise de acopladores capacitados para transceptores PLC SISO (single input single output) banda larga e banda estreita. Para tanto, são introduzidos acopladores PLC nas seguintes faixas de frequências: de 9 kHz `a 2 MHz, de 1,7 MHz `a 100 MHz e de 1,7 MHz `a 150 MHz. As análises dos projetos e dos protótipos dos acopladores, concebidos para operar nas referidas bandas, mostram as dificuldades encontradas para garantir que as especificações de projeto sejam atendidas quando os componentes passivos são comerciais e a faixa de frequência de operação do acoplador aumenta. Além disso, as análises confirmam a necessidade de consideração de técnicas de prototipação de placas de circuitos impresso para sinais de frequência elevada. Finalmente, os resultados de medição mostram que os acopladores para baixa frequência discutidos podem ser utilizados em sistemas de medição de canais PLC. / Currently, there is a great interest to develop power line communications (PLC) transceivers for broadband and narrowband data communications for smart grids and network access. However, for advancing PLC technologies, there is a great demand for introduction of couplers for connecting the PLC tranceivers to the electric energy circuits with minimum distortion. This contribution addresses the study, investigation, specification, design, and analysis of capacitive couplers for single input single output (SISO), broadband and narrowband PLC transceivers. Capacity and SISO PLC couplers covering the following frequencies bandwidth are addressed: from 9 kHz up to 2 MHz, from 1,7 MHz up to 100 MHz and from 1,7 MHz up to 150 MHz. The analysis performance of the designed and prototyped PLC couplers for operating in the aforementioned frequencies bandwidths, shows the inherent difficulties to guarantee that the design specifications are fulfilled when passive components are commercial ones and the frequency bandwidth increase. Additionally, the analysis confirms the need for taking into account advancing prototyping techniques for dealing with high-frequency signals. Finally, the measurements show that the discussed narrowband PLC couplers can be used in a PLC channel system.

Indiana University-Purdue University Indianapolis (IUPUI) / Neural signal processing to decode neural activity has been an active research area in the last few decades. The next generation of advanced multi-electrode neuroprosthetic devices aim to detect a multiplicity of channels from multiple electrodes, making the relatively time-critical processing problem massively parallel and pushing the computational demands beyond the limits of current embedded digital signal processing (DSP) techniques. To overcome these limitations, a new hybrid computational technique was explored, the Extended Analog Computer (EAC). The EAC is a digitally confgurable analog computer that takes advantage of the intrinsic ability of manifolds to solve partial diferential equations (PDEs). They are extremely fast, require little power, and have great potential for mobile computing applications. In this thesis, the EAC architecture and the mechanism of the formation of potential/current manifolds was derived and analyzed to capture its theoretical mode of operation. A new mode of operation, resistance mode, was developed and a method was devised to sample temporal data and allow their use on the EAC. The method was validated by demonstration of the device solving linear diferential equations and linear functions, and implementing arbitrary finite impulse response (FIR) and infinite impulse response (IIR) linear flters. These results were compared to conventional DSP results. A practical application to the neural computing task was further demonstrated by implementing a matched filter with the EAC simulator and the physical prototype to detect single fiber action potential from multiunit data streams derived from recorded raw electroneurograms. Exclusion error (type 1 error) and inclusion error (type 2 error) were calculated to evaluate the detection rate of the matched filter implemented on the EAC. The detection rates were found to be statistically equivalent to that from DSP simulations with exclusion and inclusion errors at 0% and 1%, respectively.