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Mankind's ability to predict weather on earth has been greatly enhanced by new instrumentation technology. Similarly, mankind's ability to predict space weather benefits from new technologies. Just as increasing the amount of atmospheric measurements on earth heightened mankind's ability to predict Earth weather, many scientists expect that expanding the amount of plasma measurements in space could be key to enhancing mankind's ability to predict space weather. Small satellites are one of these new technologies that have the potential to greatly enhance our ability to predict space weather. Utilizing many low-cost small satellites allows scientists to take data from more locations than possible with a few high-cost large satellites. Two instruments that have historic use measuring plasma are the Retarding Potential Analyzer and the Ion Drift Meter. Previous work has been done to combine the functionality from both of these instruments into one unit suitable for a small satellite in terms of size, power, and mass. An electrical and mechanical design has been completed to this end and this new instrument is called the Gridded Retarding Ion Distribution Sensor. This thesis describes the design and testing of the FPGA code that runs this new instrument.

Microphone arrays are becoming increasingly integrated into every facet of life. From sonar to gunshot detection systems to hearing aids, the performance of each system is enhanced when multi-sensor processing is implemented in lieu of single sensor processing. Head mounted microphone arrays have a broad spectrum of uses that follow the rigorous demands of human hearing. From noise cancellation to focused listening, from localization to classification of sound sources, any and all attributes of human hearing may be augmented through the use of microphone arrays and signal processing algorithms. Placing a set of headphones on a human provides several desirable features such as hearing protection, control over the acoustic environment (via headphone speakers), and a means of communication. The shortcoming of headphones is the complete occlusion of the pinnae (the ears), disrupting auditory cues utilized by humans for sound localization. This thesis presents the underlying theory in designing microphone arrays placed on diffracting bodies, specifically the human head. A progression from simple to complex geometries chronicles the effect of diffracting structures on array manifold matrices. Experimental results validate theoretical and computational models showing that arrays mounted on diffracting structures provide better beamforming and localization performance than arrays mounted in the free field. Data independent, statistically optimal, and adaptive beamforming methods are presented to cover a broad range of goals present in array applications. A framework is developed to determine the performance potential of microphone array designs regardless of geometric complexity. Directivity index, white noise gain, and singular value decomposition are all utilized as performance metrics for array comparisons. The biological basis for human hearing is presented as a fundamental attribute of headset array optimization methods. A method for optimizing microphone locations for the purpose of the recreation of HRTFs is presented, allowing transparent hearing (also called natural hearing restoration) to be performed. Results of psychoacoustic testing with a prototype headset array are presented and examined. Subjective testing shows statistically significant improvements over occluded localization when equipped with this new transparent hearing system prototype. / Ph. D.

The ever expanding range of applications for embedded systems continues to offer new challenges (and opportunities) to chip manufacturers. Applications ranging from exciting high resolution gaming to routine tasks like temperature control need to be supported on increasingly small devices with shrinking dimensions and tighter energy budgets. These systems benefit greatly by having the capability to operate over a wide range of supply voltages, known as ultra dynamic voltage scaling (U-DVS). This refers to systems capable of operating from nominal voltages down to sub-threshold voltages. Memories play an important role in these systems with future chips estimated to have over 80% of chip area occupied by memories. This thesis presents the design and characterization of an ultra dynamic voltage scalable memory (SRAM) that functions from nominal voltages down to sub-threshold voltages without the need for external support. The key contributions of the thesis are as follows: 1) A variation tolerant reference generation for single ended sensing: We present a reference generator, for U-DVS memories, that tracks the memory over a wide range of voltages and is tunable to allow functioning down to sub-threshold voltages. Replica columns are used to generate the reference voltage which allows the technique to track slow changes such as temperature and aging. A few configurable cells in the replica column are found to be sufficient to cover the whole range of voltages of interest. The use of tunable delay line to generate timing is shown to help in overcoming the effects of process variations. 2) Random-sampling based tuning algorithm: Tuning is necessary to overcome the in-creased effects of variation at lower voltages. We present an random-sampling based BIST tuning algorithm that significantly speed-up the tuning ensuring that the time required to tune is comparable to a single MBIST algorithm. Further, the use of redundancy after delay tuning enables maximum utilization of redundancy infrastructure to reduce power consumption and enhance performance. 3) Testing and Characterization for U-DVS systems: Testing and characterization is an important challenge in U-DVS systems that have remained largely unexplored. We propose an iterative technique that allows realization of an on-chip oscilloscope with minimal area overhead. The all digital nature of the technique makes it simple to design and implement across technology nodes. Combining the proposed techniques allows the designed 4 Kb SRAM array to function from 1.2 V down to 310 mV with reads functioning down to 190 mV. This would contribute towards moving ultra wide voltage operation a step closer towards implementation in commercial designs.