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Emitter identification using optical processorsHartup, David Carl 12 1900 (has links)
No description available.
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Optically interconnected parallel processor arraysDrabik, Timothy J. 12 1900 (has links)
No description available.
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Opto-electronic class AB microwave power amplifier using photoconductive switch technologyHuang, Chih-Jung, January 2006 (has links)
Thesis (Ph.D.)--University of Missouri-Columbia, 2006. / The entire dissertation/thesis text is included in the research.pdf file; the official abstract appears in the short.pdf file (which also appears in the research.pdf); a non-technical general description, or public abstract, appears in the public.pdf file. Title from title screen of research.pdf file viewed on (April 26, 2007) Vita. Includes bibliographical references.
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Array processing techniques for interference suppression in mobile communications systemsSchodorf, Jeffrey Brian 05 1900 (has links)
No description available.
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An analysis of alpha-particle-induced soft errors in high-density dynamic random-access memory arraysPerry, Reginald Jon 05 1900 (has links)
No description available.
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Inner-product based signal processing algorithms and VLSI implementation.Chen, Chiung-Hsing. January 1994 (has links)
Thesis (Ph. D.)--Ohio University, June, 1994. / Title from PDF t.p.
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A reconfigurable neural network for industrial sensory systems /Leung, Yiu-cheung. January 2000 (has links)
Thesis (M. Phil.)--University of Hong Kong, 2001. / Includes bibliographical references.
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Recovery from transient faults in wavefront processor arrays /Murthy, Vinay, January 1993 (has links)
Thesis (M.S.)--Virginia Polytechnic Institute and State University, 1993. / Vita. Abstract. Includes bibliographical references (leaves 88-91). Also available via the Internet.
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Parallel implementation of template matching on hypercube array processorsChai, Sin-Kuo January 1989 (has links)
No description available.
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A distributed control reconfiguration algorithm for 2-dimensional mesh architectures which tolerates single faults per rowWhite, Tennis S. 21 November 2012 (has links)
A reconfiguration is developed for 2-dimensional mesh architectures and applied to a fault T tolerant cellular architecture. The reconfiguration is accomplished by adding communications paths to each cell which can be enabled by means of transistor switches controlled by decoding the contents of a register containing the relative position of faulty cells. This enables faulty cells to be bypassed and operations of cells in the same row east of the faulty cell to be shifted one cell to the east and a spare cell included in the active pattern.
A modified s-value algorithm is also developed which enables a cell to determine the size of a square pattern that may be centered on that cell. / Master of Science
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