No description available.

No description available.

Thesis (Ph.D.)--University of Missouri-Columbia, 2006. / The entire dissertation/thesis text is included in the research.pdf file; the official abstract appears in the short.pdf file (which also appears in the research.pdf); a non-technical general description, or public abstract, appears in the public.pdf file. Title from title screen of research.pdf file viewed on (April 26, 2007) Vita. Includes bibliographical references.

No description available.

No description available.

Thesis (Ph. D.)--Ohio University, June, 1994. / Title from PDF t.p.

Thesis (M. Phil.)--University of Hong Kong, 2001. / Includes bibliographical references.

Thesis (M.S.)--Virginia Polytechnic Institute and State University, 1993. / Vita. Abstract. Includes bibliographical references (leaves 88-91). Also available via the Internet.

A reconfiguration is developed for 2-dimensional mesh architectures and applied to a fault T tolerant cellular architecture. The reconfiguration is accomplished by adding communications paths to each cell which can be enabled by means of transistor switches controlled by decoding the contents of a register containing the relative position of faulty cells. This enables faulty cells to be bypassed and operations of cells in the same row east of the faulty cell to be shifted one cell to the east and a spare cell included in the active pattern. A modified s-value algorithm is also developed which enables a cell to determine the size of a square pattern that may be centered on that cell. / Master of Science

Cellular arrays of processors are suitable for implementing algorithms that have a substantial amount of inherent parallelism. This thesis describes an algorithm for growing interconnection paths between processors in order to map a pattern on a fault tolerant multiprocessor array. The array uses an eight port routing switch whose hardware design and simulation is discussed in the research. The time taken to grow the paths using the proposed algorithm is evaluated with the help of timing equations derived in this thesis. Finally the effect of reducing switch hardware is investigated at both the switch level and the system level. The effect at the system level is evaluated by mapping seven different array patterns on the array and doing a probability analysis to estimate the number of switch failures required to cause array reconfiguration. It is shown that although reduction in switch hardware increases the individual switch reliability, it has a detrimental effect on the system reliability. It is also seen that the probability of array reconfiguration increases with time and pattern size. / Master of Science