Recent advances in VLSI technology have stimulated research efforts in the area of highly reliable fault tolerant, general purpose computing systems, notably, parallel systems. An automatically reconfigurable, fault-tolerant, parallel architecture is suited to VLSI technology. The architecture, a uniformly interconnected array of identical cells, is capable of functional reconfiguration as well as fault reconfiguration. Microprocessor cells are suggested as the "fabric" for implementation of the array. This thesis also introduces an I/O algorithm as an extension to the reconfiguration process, and outlines the steps by which the array cells construct paths from the active-array to the cellular array I/O ports. Path reconfiguration is presented as the method by which fault-free paths replace faulty paths. A testing algorithm is described for use in the self-testing operation of the array. The types of tests that are conducted on cells are outlined, and the basis by which a cell determines the faulty or fault-free status of a cell is described. / M.S.

The CSPI mini-MAP array processor is supported for use with a RATFOR preprocessor in the software environment defined by the Generalized Image Processing System (GIPSY). A set of interface routines presents the mini-MAP as a tightly-coupled slave processor with well-defined rules for control from the host computer. The slave is programmed by adapting host-based software, using a proscribed set of guidelines for conversion. A software protocol has been defined to allow mini-MAP data memory to be allocated dynamically. Several examples of modified GIPSY commands are examined. / Master of Science

Precise radiation pattern control for an array antenna requires precise control of array element excitations. One application is that of low side lobe patterns. Classical synthesis methods for the desired pattern may not be realized in practice due to coupling effects. Coupling occurs in two forms: the mutual coupling between array elements and the coupling introduced by the feed networks. Ideally one could account for such coupling within the array architecture during the design process and alter the feed network parameters to adjust for such coupling. Unfortunately, this is a nonlinear problem requiring special solution techniques. This report presents the solution techniques for determining feed network parameter values that compensate for antenna-feed network coupling. Scattering parameter representations of the antenna array and the feed networks are used. Examples of various array configurations for microstrip antenna arrays and for dipole arrays are included. / Master of Science

This thesis discusses a new approach to tracking the REMUS 100 AUV using a modified version of the Florida Atlantic University (FAU) ultrashort baseline (USBL) acoustic positioning system (APS). The REMUS 100 is designed to utilize a long baseline (LBL) acoustic positioning system to obtain positioning data in mid-mission. If the placement of one of the transponders of the LBL field is known, then tracking the position of the REMUS 100 AUV using a passive USBL array is possible. As part of the research for this thesis, the FAU USBL system was used to find a relative range between the REMUS 100 ranger and a LBL transponder. This relative range was then combined with direction of arrival information and LBL field component position information to determine an absolute position of the REMUS 100 ranger. The outcome was the demonstration of a passive USBL based tracking system. / by Kyle L. Seaton. / Thesis (M.S.C.S.)--Florida Atlantic University, 2013. / Includes bibliography. / Mode of access: World Wide Web. / System requirements: Adobe Reader.

With the advance of the VLSI technology, the FFT algorithm has been pushed further in solving the multidimensional array signal processing in real time. Many DSP chip users have tried to find ways to improve addressing huge data in multidimension systems with minimum cost and maximum performance. However, there is no efficient method to address data for 1-D to M-D FFTs. A methodology has been defined to conquer the addressing problem ofM-D FFT. It is well known that the twiddle factor matrix of Discrete Fourier Transform (DFT) can be recursively factored into basic butterfly stage matrices. The matrix can be factored into three matrices practically specifying the input data, twiddle factor, and output data sequence of the Fast Fourier Transform (FFT). The equivalent relationship of these matrices will be introduced. The equivalent relationship for a variety of the FFT algorithms can be obtained by equivalent transformations. Furthermore, the multidimensional (M-D) FFT can be represented by the same vector-matrix form as the one-dimensional (1-D) FFT. In addition, the addressing sequences of the 1-D FFT is a subset of the M-D FFT. Therefore, the signal flow graph of the 1-D FFT can be used to describe that of the M-D FFT and all M-D indexing can be implemented by 1-D indexing. Finally, this unified indexing approach was implemented into the WinDSP software simulator. Examples of M-D FFTs implemented with the unified indexing method are simulated on the WinDSP and the computation performance were analyzed. From the benchmark analysis, the 2-D FFT applications implemented with unified methodology use less instructions and the execution time is almost two times faster than the traditional method. WinDSP is a software simulator that simulates the functional characteristics of Sharp LH9124/LH9320 DSP chip set. It intended to manage the complete development of DSP applications, from conceptualization and experimentation, to verification of unified indexing for 1-D to M-D FFT. It is also intended for system development, where hardware can be implemented for the design.

Fully efficient systolic arrays for the solution of Toeplitz matrices using Schur algorithm [1] have been obtained. By applying clustering mapping method [2], the complexity of the algorithm is 0(n) and it requires n/2 processing elements as opposed to n processing elements developed elsewhere [1]. The motivation of this thesis is to obtain efficient pipeline arrays by using the synthesis procedure to implement Toeplitz matrix solution. Furthermore, we will examine pipeline structures for the Toeplitz system factorization and back-substitution by obtaining clustering and Multi-Rate Array structures. These methods reduce the number of processing elements and enhance the computational speed. Comparison and advantage of these methods to other method will be presented. / Graduation date: 1992

Many systematic methods exist for mapping algorithms to processor arrays. The algorithm is usually specified as a set of recurrence equations, and the processor arrays are synthesized by finding timing and allocation functions which transform index points in the recurrences into points in a space-time domain. The problem of scheduling (i.e. finding the timing function) of recurrence equations has been studied by a number of researchers. Of particular interest here are Systems of Affine Recurrence Equations (SAREs). The existing methods are limited to affine (or linear) schedules over the entire domain of computation. For some algorithms, there are points in the computation domain where the dependencies point in opposite directions, and an affine schedule does not exist, although a valid Piecewise Affine Schedule (PAS) can exist. The objective of this thesis is to examine these schedules and obtain a systematic method for deriving such schedules for SAREs. PAS can be found by first partitioning the computation domain and then obtaining a new SARE by renaming the variables. By partitioning the computation domain, we can obtain additional parallelism from the dependency graph, and find faster schedules over subspaces of the domain. In this paper, we describe a procedure for partitioning the domain and to generate a new SARE by renaming the variables. Some heuristics are introduced for partitioning the domain based on the properties of dependence vectors. After the partitioning and renaming, an existing method (due to Mauras et al.) is applied to find the schedules. Examples of Toeplitz System and Algebraic Path Problem are used to illustrate the results. / Graduation date: 1992

Thesis (Ph. D.)--State University of New York at Binghamton, Department of Systems Science and Industrial Engineering, Thomas J. Watson School of Engineering and Applied Science, 2007. / Includes bibliographical references.

Thesis (MTech (Electrical Engineering))--Cape Peninsula University of Technology, 2008. / Includes bibliographical references (leaves 335-340). Also available online.

Thesis (Ph.D.)--McMaster University, 2004. / Advisor: James P. Reilly. Includes bibliographical references ( leaves 204-213). Also available online.