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  • About
  • The Global ETD Search service is a free service for researchers to find electronic theses and dissertations. This service is provided by the Networked Digital Library of Theses and Dissertations.
    Our metadata is collected from universities around the world. If you manage a university/consortium/country archive and want to be added, details can be found on the NDLTD website.
1

Emitter identification using optical processors

Hartup, David Carl 12 1900 (has links)
No description available.
2

Optically interconnected parallel processor arrays

Drabik, Timothy J. 12 1900 (has links)
No description available.
3

Opto-electronic class AB microwave power amplifier using photoconductive switch technology

Huang, Chih-Jung, January 2006 (has links)
Thesis (Ph.D.)--University of Missouri-Columbia, 2006. / The entire dissertation/thesis text is included in the research.pdf file; the official abstract appears in the short.pdf file (which also appears in the research.pdf); a non-technical general description, or public abstract, appears in the public.pdf file. Title from title screen of research.pdf file viewed on (April 26, 2007) Vita. Includes bibliographical references.
4

Array processing techniques for interference suppression in mobile communications systems

Schodorf, Jeffrey Brian 05 1900 (has links)
No description available.
5

An analysis of alpha-particle-induced soft errors in high-density dynamic random-access memory arrays

Perry, Reginald Jon 05 1900 (has links)
No description available.
6

Inner-product based signal processing algorithms and VLSI implementation.

Chen, Chiung-Hsing. January 1994 (has links)
Thesis (Ph. D.)--Ohio University, June, 1994. / Title from PDF t.p.
7

A reconfigurable neural network for industrial sensory systems /

Leung, Yiu-cheung. January 2000 (has links)
Thesis (M. Phil.)--University of Hong Kong, 2001. / Includes bibliographical references.
8

Recovery from transient faults in wavefront processor arrays /

Murthy, Vinay, January 1993 (has links)
Thesis (M.S.)--Virginia Polytechnic Institute and State University, 1993. / Vita. Abstract. Includes bibliographical references (leaves 88-91). Also available via the Internet.
9

Parallel implementation of template matching on hypercube array processors

Chai, Sin-Kuo January 1989 (has links)
No description available.
10

An algorithm for growing interconnection paths in a fault tolerant multiprocessor array

Zaidi, Syed Ahmad Abbas January 1987 (has links)
Cellular arrays of processors are suitable for implementing algorithms that have a substantial amount of inherent parallelism. This thesis describes an algorithm for growing interconnection paths between processors in order to map a pattern on a fault tolerant multiprocessor array. The array uses an eight port routing switch whose hardware design and simulation is discussed in the research. The time taken to grow the paths using the proposed algorithm is evaluated with the help of timing equations derived in this thesis. Finally the effect of reducing switch hardware is investigated at both the switch level and the system level. The effect at the system level is evaluated by mapping seven different array patterns on the array and doing a probability analysis to estimate the number of switch failures required to cause array reconfiguration. It is shown that although reduction in switch hardware increases the individual switch reliability, it has a detrimental effect on the system reliability. It is also seen that the probability of array reconfiguration increases with time and pattern size. / Master of Science

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