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  • About
  • The Global ETD Search service is a free service for researchers to find electronic theses and dissertations. This service is provided by the Networked Digital Library of Theses and Dissertations.
    Our metadata is collected from universities around the world. If you manage a university/consortium/country archive and want to be added, details can be found on the NDLTD website.
1

The super-actor machine : a hybrid dataflowvon Neumann architecture

Hum, Herbert Hing-Jing January 1992 (has links)
Emerging VLSI/ULSI technologies have created new opportunities in designing computer architectures capable of hiding the latencies and synchronization overheads associated with von Neumann-style multiprocessing. Pure Dataflow architectures have been suggested as solutions, but they do not adequately address the issues of local memory latencies and fine-grain synchronization costs. In this thesis, we propose a novel hybrid dataflow/von Neumann architecture, called the Super-Actor Machine, to address the problems facing von Neumann and pure dataflow machines. This architecture uses a novel high-speed memory organization known as a register-cache to tolerate local memory latencies and decrease local memory bandwidth requirements. The register-cache is unique in that it appears as a register file to the execution unit, while from the perspective of main memory, its contents are tagged as in conventional caches. Fine-grain synchronization costs are alleviated by the hybrid execution model and a loosely-coupled scheduling mechanism. / A major goal of this dissertation is to characterize the performance of the Super-Actor Machine and compare it with other architectures for a class of programs typical of scientific computations. The thesis includes a review on the precursor called the McGill Dataflow Architecture, description of a Super-Actor Execution Model, a design for a Super-Actor Machine, description of the register-cache mechanism, compilation techniques for the Super-Actor Machine and results from a detailed simulator. Results show that the Super-Actor Machine can tolerate local memory latencies and fine-grain synchronization overheads--the execution unit can sustain 99% throughput--if a program has adequate exposed parallelism.
2

Floating-point fused multiply-add architectures

Quinnell, Eric Charles 28 August 2008 (has links)
Not available / text
3

Floating-point fused multiply-add architectures

Quinnell, Eric Charles, 1982- 22 August 2011 (has links)
Not available / text
4

The design and programming of a powerful short-wordlength processor using context-dependent machine instructions

Hor, Tze-man, 賀子文 January 1985 (has links)
published_or_final_version / Computer Science / Master / Master of Philosophy
5

The design and programming of a powerful short-wordlength processor using context-dependent machine instructions /

Hor, Tze-man. January 1985 (has links)
Thesis--M. Phil., University of Hong Kong, 1985.
6

Viable software : the intelligent control paradigm for adaptable and adaptive architecture /

Herring, Charles Edward. January 2002 (has links)
Thesis (Ph. D.)--University of Queensland, 2002. / Includes bibliographical references.
7

Design of North Texas PC Users Group ecommerce interface and online membership system professional project /

Steele, Jeri J. January 2006 (has links) (PDF)
Thesis (M.S.C.I.T.)--Regis University, Denver, Colo., 2006. / Title from PDF title page (viewed on Apr. 7, 2006). Includes bibliographical references.
8

A dual-ported real memory architecture for the g-machine

Rankin, Linda J. 08 1900 (has links) (PDF)
M.S. / Computer Science & Engineering / A dual-ported real memory architecture is described which supports the requirements of a list-processing evaluator, the G-machine. The architecture provides support for allocating available nodes and a concurrent garbage collection scheme. This scheme uses reference counts and requires traversal of sub-graphs to collect cyclic structures. The architecture requires only one customized hardware component that provides support for maintaining reference counts. Simulation of the architecture shows that it is efficient and meets the requirements of the G-machine given certain assumptions about the number and size of sub-graphs that are traversed. Cyclic structure information provided by the compiler would reduce the number of sub-graphs requiring traversal. Simulation shows that this optimization improves performance of the design, particularly for allocation rates greater than 100K nodes per second.
9

Design of energy-efficient application-specific instruction set processors /

Glökler, Tilman. Meyr, Heinrich. January 2004 (has links)
Techn. Hochsch., Diss. u.d.T.: Glökler, Tilman: Design of energy-efficient application-specific instruction set processors (ASIPs)--Aachen, 2003.
10

Floating-point fused multiply-add architectures

Quinnell, Eric Charles, January 1900 (has links)
Thesis (Ph. D.)--University of Texas at Austin, 2007. / Vita. Includes bibliographical references.

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