Atomic layer deposition (ALD) has emerged as an important technique for depositing thin films in both scientific research and industrial applications. The goal of this work is to integrate functional materials using ALD including high-κ dielectric, LaAlO₃, ferroelectric BaTiO₃, photocatalytic CoO, and room temperature ferromagnetic thin films of Co metal for spin-transfer torque random-access memory applications. The work is also to demonstrate the formation of a quasi-two-dimensional electron gas (2-DEG) at the γ-Al₂O₃/SrTiO₃ heterointerface enabling a method for all-oxide device manufacturing using ALD. High permittivity oxide thin films are needed to replace SiO₂ in complementary metal oxide semiconductor (CMOS) transistors. The replacement of SiO₂ by hafnium oxide-based high-κ materials in CMOS devices in 2007 was a revolutionary development in semiconductor front end of line. The continued device feature shrinking requires higher-κ dielectrics, compared to HfO₂-based materials. Crystalline perovskite oxides, such as SrTiO₃, LaAlO₃, and BaTiO₃, etc. have from high to very high dielectric constant and being proposed to replace HfO₂-based materials in CMOS devices if the leakage problem is resolved. The work explores the monolithic integration of crystalline perovskite oxide films with Si(001) using combined molecular beam epitaxy (MBE) and ALD techniques. Four unit cells of SrTiO₃ were grown directly on Si(001) by MBE and transferred in-situ into the ALD chamber for further depositions. The integration of oxide thin films on Si(001) using the MBE-ALD technique allows us to maintain clean oxide/Si(001) interfaces since low temperatures (180–250 °C) were maintained during the ALD deposition. The goal of my work is also to explore processes to enable area selective deposition of cobalt (II) oxide, CoO. The effectiveness of poly(trimethylsilylstyrene) in selectively inhibiting surface nucleation of CoO on SiO₂ and MgO substrates is demonstrated. Carbon-free cobalt thin films are formed by reducing CoO using Al and Sr metals to scavenge oxygen from CoO. The work explores the ability to control the structure and morphology of the resultant cobalt film by tuning the reduction conditions, allowing us to tune magnetic properties of the cobalt thin film. My work also focuses on the growth of γ-Al₂O₃ on the TiO₂-terminated SrTiO₃ substrate at temperatures higher than 300 °C. The formation of a quasi-2-DEG is found at the γ-Al₂O₃/TiO₂-terminated SrTiO₃ interface. In-situ x-ray photoelectron spectroscopy reveals the presence of Ti³⁺ feature at the heterointerface. Conductivity at the interface was found to be proportional to the amount of Ti³⁺ species. Oxide quasi-2-DEG might provide opportunities for new generations of all-oxide electronic devices using ALD.

The past decade and a half has seen the rapid emergence of a new material class known as photonic crystals (PCs), structures that exhibit 1, 2, or 3, dimensional periodicity of their dielectric constant, resulting in a modification of the dispersion characteristics from the normal w = vk relationship found in isotropic materials. Several remarkable electromagnetic phenomenon result, including the formation of photonic band gaps (PBGs), which are specific energy ranges where electromagnetic wave propagation is forbidden, and the existence of energies where the photon group velocity is slowed drastically from its normal value. The resulting modification of a materials photonic band structure allows unprecedented control of light, resulting in phenomena such as self-collimation, and spontaneous emission modification or lasing threshold reduction through either band edge effects (low group velocity) or microcavity defect incorporation. PCs for operation at visible wavelengths are difficult to form due to the need for nanoscale fabrication techniques. The research described focused on the fabrication of photonic crystal phosphors by using the infiltration and subsequent removal of self-assembled opal templates to make inverted opal-based photonic crystals. This thesis shows the advantages that atomic layer deposition (ALD) has as an important method for use in photonic crystal fabrication, and highlights the exciting results of use of ALD to fabricate luminescent ZnS:Mn and optically inactive titania inverse opals, as well as ZnS:Mntitania luminescent composite inverse opals.

Abstract High quality epitaxial growth of undoped ZnSe, ZnSxSe1-x and ZnSe-ZnS strained quantum well structures were successfully grown on n-type (100)-oriented silicon substrates at 150 ºC in a horizontal cold-wall quartz reactor by low-pressure metalorganic atomic layer epitaxy (MOALE) at a pressure of 30 Torr for the first time. Dimethylzinc [Zn(CH3)2, DMZn], hydrogen selenide (H2Se) and hydrogen sulfur (H2S) were used as the reactants. ALE is a suitable technique for the growth of ultra thin semiconductors because it provides accuracy monolayer control of the deposited film thickness, low growth temperature and uniform growth over a large area by its¡§ self-limiting mechanism ¡¨via supplying source materials in a flow pulse sequences alternatively over the substrate. Idea one monolayer per cycle was obtained in wide range of parameters such as substrate temperatures, mole flow rate and pulse duration of reactants. From X-ray diffraction pattern, (400)-oriental single crystal epilayers of ZnSe are evidenced. The surface morphologies of ZnSe in the ALE temperature region 150 - 200 ¢J, extensively smooth and mirror-like surface were obtained. PL spectra of ZnSe epilayer is dominated by the strong near-band-edge at 2.8 eV with FWHM of 36 meV. Schottky diodes were fabricated from the undoped ZnSe layer and the electrical properties were measured at room temperature. From the current-voltage (I-V) characteristics, a high reverse breakdown voltage (>40 V) and an excellent low cut-in voltage of 0.6 - 0.8 V were obtained. On the basis of the observed ZnSe/Si epitaxial film properties, the material is suitable for fabrication of ZnSe-based blue light emitting diodes and for application in direct-current thin-film electroluminescence. The lattice of the ZnSxSe1-x layer with a sulfur content around 93% was found to have the best match to the Si substrate, as confirmed by the good layer thickness, uniformity, surface morphology and narrow linewidth of the X-ray diffraction rocking curve with a minimal FWHM of about 0.16 degree. In addition, strong near-band-edge and weak deep-level emissions in the longer wavelength region dominate PL spectra of the ZnS0.93Se0.07 epilayer at 300K. With respect to Schottky diodes, Au/n-ZnS0.93Se0.07/Al, has a high breakdown voltage, over 40 V at 400 nA and a low cut-in voltage of 0.68 V. The highest Hall mobility of the ZnS0.93Se0.07 is 347 cm2/v-sec. These results indicate a good lattice-match of ZnS0.93Se0.07/Si as a result of low numbers of interface and epitaxial layer defects. The lower temperature of ZnSe-ZnS strained quantum well structures, 150 ºC would be lowed enough to eliminate 3-D growth related to the lattice mismatch between ZnSe and ZnS. A good epitaxy and crystallinity was carried out by X-ray diffraction. The formation of the strained quantum well structure is evident from the periodic behavior of each fluctuation profile by SIMS. At least 25 periodic thickness of the ALE growth samples shows a strong blue emissions and nearly neglects the deep-level emission at room temperature. The phenomenon of quantum size effects and the ¡§ blue-shift ¡¨ was evidenced as the well width increases. The results of the PL measurements were found to correlate well with the theoretical one, parabolic well-strain mode. Schottky diodes were fabricated from the Au/ZnSe-ZnS SMQW/n-Si/Al, a high reverse breakdown voltage over 40 (at 20 µA) and an extremely low cut-in voltage of 80 - 120 mV were obtained. The I-V characteristics of the heterojunction are more suitable for the fabrication of the direct-current thin film electroluminescent (EL) device.

Atomic Layer Epitaxy is a stepwise deposition process by supplying the sources materials alternatively. This deposition technique provides the monolayer control of film thickness and the uniform film growth over a large area. ZnSxSe1-x layers were grown epitaxially onto Si and GaAs substrate by using DMZn and H2S , H2Se gases for the reactant source. Owing to the self-limiting characteristics of ALE process, ZnSxSe1-x monolayers could be deposited over a wide range of temperature within growth window. In this study, for obtaining high crystalline quality ZnSxSe1-x epitaxial films, various growth conditions were investigated including substrate temperature, the flow rate of DMZn, H2S and H2Se, H2 purge duration and pulse duration etc.. A thermodynamic analysis based the calculation of Seki et. al [6], was used to investigate the effects by varying the substrate temperature, input mole ratio of group VI source gases on equilibrium partial pressure, solid composition and solid-vapor distribution relation of this alloy. The interaction parameter of ZnSxSe1-x, £[, was estimated by using the delta-lattice parameter (DLP) model suggested by Stringfellow [39]. Finally, it shows that the thermodynamic analysis provides a useful guideline for the growth of ZnSxSe1-x alloy on Si and GaAs substrates.

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The growth of single and multilayer BN films on several substrates was investigated. A typical atomic layer deposition (ALD) process was demonstrated on Si(111) substrate with a growth rate of 1.1 Å/cycle which showed good agreement with the literature value and a near stoichiometric B/N ratio. Boron nitride films were also deposited by ALD on Cu poly crystal and Cu(111) single crystal substrates for the first time, and a growth rate of ~1ML/ALD cycle was obtained with a B/N ratio of ~2. The realization of a h-BN/Cu heterojunction was the first step towards a graphene/h-BN/Cu structure which has potential application in gateable interconnects.

<p dir="ltr">As silicon (Si) technology advances to 3 nm node and beyond, vertically stacking in 3D is considered as the primary choice to increase the density of transistors per unit area for better chip performance. Therefore, looking for new materials capable of replacing Si in back-end-of-line (BEOL) compatible monolithic 3D (M3D) integration has become one of the most important topics in the current field of electronic devices. Recent developed atomic layer deposition (ALD) deposited indium oxide (In₂O₃) field-effect transistors (FETs) have realized excellent electrical performance including field effect mobility over 100 cm²/V·s, on/off ratio up to 10¹⁷ and on-state current (I_ON) over 2.5 mA/μm in nanometer thin In₂O₃ FETs, providing promising prospect for next generation electronics. In this thesis, four main In₂O₃ related topics are discussed to examine the practicality of ALD In₂O₃ as channel material in BEOL compatible applications. First, the bias stability of planar In₂O₃ transistors and the effect of tin doping are studied. Second, gate-all-around (GAA) In₂O₃ FETs are implemented to improve I_ON up to record high 20 mA/μm, and its reliability is systematically measured and analyzed. Third, multilayer In₂O₃ FETs are constructed to investigate the possibility of vertical stacking. Last, vertical full oxide transistors with In₂O₃ gate are demonstrated to prove the feasibility of potential 3D integration.</p>

This work seeks to apply the novel heat flux sensor called as the Atomic Layer Thermopile to measure high frequency heat flux in high speed and high temperature flows found in Gas Turbine combustors. To achieve this the sensor must be able to survive the harsh environment of high temperature and high pressure. To have any confidence in our measurement, it is also imperative that there are tools available for precise estimation of the measurement uncertainty. This works strives to achieve these objectives by developing calibration techniques for uncertainty estimation using both exposure to radiation and in convective environments by calibrating against power input in steady state flow and transient heat flux calculated using wall temperature measurement. The response of the sensor is then investigated in high speed flows by measuring the heat flux inside a supersonic nozzle when exposed to shock waves. The shock waves are generated using a fast throttle valve located at the entrance of the supersonic nozzle by generating sudden rise in pressure. Lastly a numerical study is carried out to design a cooling system that will allow the sensor to survive in high temperature conditions of 1000°C while the sensor film is maintained at 50°C. A one-dimensional model is used to provide initial design parameters and then a two-dimensional axisymmetric conjugate CFD analysis is carried out to obtain the desired geometry that can meet the design conditions. A static structural analysis is also carried out on this geometry to ensure that it will be able to survive and avoid distortion under the operational pressure required for providing the desired coolant mass flow.

Inside your microelectronic devices there are up to a billion transistors working in flawless operation. Silicon has been the workhorse semiconductor used for the transistor; however, there must be a transition to materials other than silicon, such as germanium, with future device sizes. In addition, new dielectric oxide materials are needed. My research has examined a type of crystalline oxide, known as a perovskite, which is selected for its ability to bond chemically to Si and Ge, and eliminate the electrical defects that affect performance. Many perovskite oxides are lattice-matched to the Si (001) and Ge (001) surface spacing, enabling heteroepitaxy. To date, the majority of research on crystalline oxides integrated with semiconductors has been based on strontium titanate, SrTiO3, epitaxially grown on Si (001) by molecular beam epitaxy. Alternative low-temperature growth methods, such as atomic layer deposition (ALD), offer both practical and economic benefits for the integration of crystalline oxides on semiconductors. My initial research informed the broader community that four unit cells (~1.5 nm) of SrTiO3 are required to enable heteroepitaxy on Si. The research has also shown that heteroepitaxial layers can be monolithically integrated with Si (001) without the formation of a SiOx interlayer between the Si (001) surface and the SrTiO3 layer because ALD is performed at lower temperatures than are typical for MBE. Thus, a combined MBE-ALD growth technique creates possible advantages in device designs that require the crystalline oxide to be in contact with the Si (001) surface. In recent work, I have demonstrated a method for integrating crystalline oxides directly on Ge by ALD. Germanium is being explored as an alternative channel material due to its higher hole and electron mobilities than Si, potentially enabling device operation at higher speed. This all-chemical growth process is expected to be scalable, is inherently less costly from a manufacturing cost of ownership, and is based on current manufacturing tool infrastructure. The impact of my research will be in continued scaling of device dimensions with novel materials that will provide faster speed and lower power consumption for microelectronic devices. / text