Thesis (Ph. D.)--University of Texas at Austin, 2000. / Vita. Includes bibliographical references (leaves 293-300). Available also in a digital version from Dissertation Abstracts.

Thesis (Ph. D.)--University of Texas at Austin, 1999. / Includes bibliographical references (leaves 108-118). Available also in a digital version from Dissertation Abstracts.

Thesis (Ph. D.)--Ohio University, November, 1992. / Title from PDF t.p.

Thesis (Ph. D.)--University of Texas at Austin, 1999. / Vita. Includes bibliographical references (leaves 108-118). Available also in a digital version from Dissertation Abstracts.

Report (M.S.)--Virginia Polytechnic Institute and State University. M.S. 1993. / Abstract. Includes bibliographical references (leaf 107). Also available via the Internet.

Thesis (Ph.D.)--University of Nebraska-Lincoln, 2006. / Title from title screen (site viewed May 23, 2007). PDF text: vi, 140 p. : ill. (some col.) ; 2.70Mb UMI publication number: AAT 3236905. Includes bibliographical references. Also available in microfilm and microfiche formats.

Incorrect system operation can, at worst, be life threatening or financially devastating. Software testing is a destructive process that aims to reveal software faults. Selection of good test data can be extremely difficult. To ease and assist test data selection, several test data generators have emerged that use a diverse range of approaches. Adaptive test data generators use existing test data to produce further effective test data. It has been observed that there is little empirical data on the adaptive approach. This thesis presents the Heuristically Aided Testing System (HATS), which is an adaptive test data generator that uses several heuristics. A heuristic embodies a test data generation technique. Four heuristics have been developed. The first heuristic, Direct Assignment, generates test data for conditions involving an input variable and a constant. The Alternating Variable heuristic determines a promising direction to modify input variables, then takes ever increasing steps in this direction. The Linear Predictor heuristic performs linear extrapolations on input variables. The final heuristic, Boundary Follower, uses input domain boundaries as a guide to locate hard-to-find solutions. Several Ada procedures have been tested with HATS; a quadratic equation solver, a triangle classifier, a remainder calculator and a linear search. Collectively they present some common and rare test data generation problems. The weakest testing criterion HATS has attempted to satisfy is all branches. Stronger, mutation-based criteria have been used on two of the procedures. HATS has achieved complete branch coverage on each procedure, except where there is a higher level of control flow complexity combined with non-linear input variables. Both branch and mutation testing criteria have enabled a better understanding of the test data generation problems and contributed to the evolution of heuristics and the development of new heuristics. This thesis contributes the following to knowledge: Empirical data on the adaptive heuristic approach to test data generation. How input domain boundaries can be used as guidance for a heuristic. An effective heuristic termination technique based on the heuristic's progress. A comparison of HATS with random testing. Properties of the test software that indicate when HATS will take less effort than random testing are identified.

This dissertation encompasses primarily design for testability (DFT) problems of concurrent checking and structural off-line Built-In Self-Test. We present a new DFT method, which employs cyclic code checking as a medium to combine the concurrent checking and signature analysis in a built-in fashion. It uses bit-sliced linear feedback shift registers (LFSRs) or linear cellular automata registers (LCARs) as the implementation mechanism. A circuit under test designed in this method supports both on-line and off-line testability with shared hardware resources. It has comparable on-line error-detecting ability to the conventional error-detecting codes and without affecting the high fault coverage of off-line signature analysis. This testing scheme complies with the IEEE boundary-scan standard and is applicable to general circuitry. Evaluations of the proposed scheme are carried out with respect to the area overhead, performance and testing time, design complexity, pin count, and fault coverage. The concatenation properties of LCARs are introduced and recent developments in related issues are reviewed. Finally, a new area estimation method for circuit design is presented to ease silicon cost measurement / Graduate

Thesis (Ph. D.)--University of Texas at Austin, 2006. / Vita. Includes bibliographical references.

Thesis (Ph. D.)--University of Texas at Austin, 2000. / Vita. Includes bibliographical references (leaves 94-100). Available also in a digital version from Dissertation Abstracts.