<p>In the field of embedded computer and communication systems, the demands for the </p><p>interconnection networks are increasing rapidly. To satisfy these demands much advancement has </p><p>been made at the chip level as well as at the system level and still the research works are going </p><p>on, to make the interconnection networks more flexible to satisfy the demands of the real-time </p><p>applications. </p><p> </p><p>This thesis mainly focuses on the interconnection between the nodes in an embedded system via a </p><p>reconfigurable backplane. To satisfy the project goals, an algorithm is written for the </p><p>reconfigurable topology that changes according to the given traffic specification like throughput. </p><p>Initially the connections are established between pairs of nodes according to the given throughput </p><p>demands. By establishing all the connections, a topology is formed. Then a possible path is </p><p>chosen for traversing the data from source to destination nodes. Later the algorithm is </p><p>implemented by simulation and the results are shown in a tabular form. Through some application </p><p>examples, we both identify problems with the algorithm and propose an improvement to deal </p><p>with such problems.</p>

In the field of embedded computer and communication systems, the demands for the interconnection networks are increasing rapidly. To satisfy these demands much advancement has been made at the chip level as well as at the system level and still the research works are going on, to make the interconnection networks more flexible to satisfy the demands of the real-time applications. This thesis mainly focuses on the interconnection between the nodes in an embedded system via a reconfigurable backplane. To satisfy the project goals, an algorithm is written for the reconfigurable topology that changes according to the given traffic specification like throughput. Initially the connections are established between pairs of nodes according to the given throughput demands. By establishing all the connections, a topology is formed. Then a possible path is chosen for traversing the data from source to destination nodes. Later the algorithm is implemented by simulation and the results are shown in a tabular form. Through some application examples, we both identify problems with the algorithm and propose an improvement to deal with such problems.

ORMOCERR®s are organic-inorganic hybrid polymers. Since their material properties can be tailored precisely during synthesis, they are suitable for a wide range of applications in dielectric and optical microelectronics. This thesis reports on process development of ORMOCERR®s for Sequentially Build-Up (SBU) test vehicles, suitable for both electrical and optical interconnect. Furthermore, this work includes materials characterization, such as refractive index studies (system B59:V32), optical loss measurements (systems B59:V32 and B59:B66), and surface characterization through contact angle measurement and surface energy estimation (systems B59:V32 and B59:B66). Process development for a high-frequency test vehicle was performed applying a newly developed dielectric material of the ORMOCER® class. Dielectric layers in a total thickness of 80 μm were build-up on a common FR4 substrate, applying photolithographic processes and moderate process temperatures of below 433 K. The loss tangent and the permittivity of the material were measured to be 0.024 (loss tangent) and 3.05 (permittivity) over the entire frequency range 10 GHz to 40 GHz. The compatibility of the material to standard processes of the PCB industry was proven. Furthermore, a possibility for cost reduction in high-frequency MCM applications was shown, through the possibility of using low-cost substrates. The concept of a “flexible manufacture approach” for large-area panel optical backplane interconnects was introduced. Here, a 101.6 mm x 101.6 mm photolithographic mask is to be stepped-out over a large-area panel substrate (up to 609.6 mm x 609.6 mm). The goal is to be able to create a large amount of continuous and unique waveguide patterns over the whole area with a small portfolio of masks, thus being able to minimize excess costs. In practice continuous waveguide patterns were created over an area of 204.8 mm x 204.8 mm on a large-are panel (609.6 mm x 609.6 mm), using a large-are mask aligner and a 101.6 mm x 101.6 mm waveguide mask. The optical loss of the waveguides was measured to be 0.6 dB/cm (B59:V32 material system, λ =850 nm). In connection to the large-area panel project a re-evaluation on the optical power budget needed for high bit rate optical interconnects was performed. This work was mainly based on literature surveys of optical waveguide materials, planar optical amplifiers, light coupling structures, and planar light-routing structures. It was shown that optical amplification is necessary at certain places on realistically routed optical backplanes to boost the optical signal. Therefore, the concept of a flip-chip mountable optical amplifier (FOWA) device, based on planar optical waveguide amplifiers and Semiconductor Optical Amplifiers, was developed. The device’s design allows an independent manufacturing to the rest of the board and a mounting at key-positions using standard pick and place technology. Additionally, it was observed that most of the amplifier research is focused on the wavelength of 1310 nm and 1550 nm, whereas optical backplane applications are targeting the 830 nm range. During SBU processing of waveguide structures was discovered a de-wetting phenomenon of B59 resin on a cured B59:B66 and B59:V32 surface, respectively. Good wetting behavior could be achieved by adding small amounts of B66 or V32, respectively, to the B59. Surface tension estimations on various compositions of the systems B59:B66 and B59:V32 could not directly be correlated to the de-wetting phenomenon. Furthermore, the optical loss properties of B59 were only affected to a minor degree by adding B66 or V32. The process route proposed is an efficient alternative to processes including surface activations steps, thus opening possibilities for large-area processing in PCB industry, where surface activation steps, such as plasma activation or silanization, are not available. The process development, materials characterization, and reviews presented provide a basis for further research on processes for high-performance electro/optical backplane interconnects with focus on Large-Area Panel processing.