Recent advances in computing technology have highlighted deficiencies with electrical interconnections at the motherboard and card-to-backplane levels. The CPU speeds of computing systems are drastically increasing with on-chip local clock speeds expected to approach 6 GHz by 2010. Yet, card-to-backplane communication speeds have been unable to maintain the same pace. At speeds beyond a few gigahertz the implementation of electronic interconnects gets increasingly complex, thus, alternative optical interconnection techniques are being extensively researched to relieve the expected CPU to data bus bottleneck. Despite the advantages afforded by optical interconnects there are still demands for improved packaging, enhanced signal tapping, and reduced cost expenditures. In this dissertation, we present a novel array waveguide evanescent coupling (AWEC) technology for card-to-backplane applications. The interconnection scheme is based on waveguide directional coupling between a backplane waveguide and a flexible waveguide connected to the access card or daughter board. To gain access to the shared bus media, coupling of evanescent waves is exploited to tap optical signals from the backplane waveguide to the corresponding card waveguide. The approach results in the elimination of micro-mirror out of plane deflectors and local waveguide termination obstacles present in other reported optical interconnect schemes. Most importantly, the AWEC method can yield efficient multi-drop bus architectures, not possible through free-space, fiber, or traditional guided wave approaches, that only achieve point-to-point topologies. The AWEC concept for optical interconnection was introduced through coupled mode theory, numerical simulations and BeamPROP aided CAD models. Subsequent experimental waveguide analysis was performed and shown to reasonably agree with the simulation results. Likewise, a high-resolution, cost-effective, and rapid prototyping approach for AWEC fabrication has been formulated. Significantly, when compared to other soft lithographic methods, the novel vacuum assisted microfluidic (VAM) technique results in improved waveguide structures, polymer background residue elimination and lower propagation losses. Moreover, experimental results show that our evanescent coupling approach facilitates high-speed coupling between card and backplane waveguides at speeds of 10 Gbps per channel; currently limited only by our testing electronics. In addition, satisfactory eye diagram performance comparable to that of a conventional fiber link, was also observed for the AWEC, alluding to possible aggregate speeds of 100 Gbps. Similarly, we implemented an elementary AWEC shared bus architecture and demonstrate a microprocessor-to-memory interconnect prototype through the proposed AWEC link. Notably, we expect that the AWEC scheme will be significant for high-speed optical interconnects in advanced computing systems.

The object of this research is to develop a solution for band-limited channels. Backplane channels and GPON channels are investigated to apply an equalization technique. Different lengths of backplane channels are measured with different signal speeds to investigate the channel performance. Also a GPON system with different fiber lengths is designed and set up in a lab to measure the BER performance. The GPON system utilizes a Fabry-Perot laser for the most economical solution. After the circuits are fabricated, they are inserted into the system to measure the performance of the channels with equalizers. Both the backplane and the GPON system show successful channel improvement in measured eye diagrams and BER. To expedite the procedure and eventually build an adaptive system which could be inserted and self-optimizing, we found it essential to monitor the output of the equalizer. A novel analog way to achieve this goal is suggested. All the equalizers mentioned in this dissertation have one summing node to add up all the values from VGAs. This structure is very efficient, but in the event that there are too many VGAs, it draws too much current through the one node. This issue is dealt with by the design of two nine tap equalizers, which are compared to assess the difference in performance between the unbalanced structure and the balanced structure.

<p>Larger systems today, like telephone and optical switches, are usually based on a multiboard architecture where a set of printed-circuit boards are connected to a backplane board. These systems are also equipped with Boundary-Scan to enable testing, however, the backplane in a multi-board system has a limited wiring capability, which makes the additional backplane Boundary-Scan wiring highly costly. The problem is to access the Boundary-Scan enabled boards with the Boundary-Scan controller located at a central board. In this MSc. thesis project we propose an approach suitable for the Advanced Telecommunication Computing Architecture (ATCA) standard where we make use of the existing Intelligent Platform Management Bus (IPMB) and expands its protocol for application of Boundary-Scan tests. We have also defined a command set as well as a test data format for storing embedded test data on the boards to support the remote execution of Boundary-Scan tests. For validation of the proposed approach we have developed demonstrator.</p>

A combined solution of the Feed-Forward Equalizer (FFE) and Near-End Crosstalk (NEXT) noise cancellation technique was suggested. The techniques increase data throughput and improve link quality in the 20-in FR4 legacy backplane application. Backplane channel loss and coupling noise were measured and characterized to develop the corresponding behavioral channel model. The receiver-side FFE with 4-tap Finite Impulse Response (FIR) filter structure was adopted as the optimum equalizer topology. The 4-tap FIR filter consists of tap delay line with tap-spacing 33 ps and linear tap-gain amplifiers. The tap coefficients were calculated with the Minimum-Mean-Squared-Error (MMSE) algorithm. A 0.18-um CMOS 4-tap FIR filter IC was designed and fabricated. The experiment results showed the 20-Gbit/sec 4-PAM and 10-Gbit/sec NRZ signal were successfully equalized for the 20-in FR4 legacy backplane channel. Moreover, the suggested NEXT noise cancellation technique consists of coarse- and fine-cancellation stages. The 0.18-um CMOS building block ICs such as 7-tap FIR filter, tunable active Pole-Zero (PZ) filter, and a temporal alignment delay line were fabricated. The experiment results showed that 6-dB Signal-to-Noise Ratio (SNR) improvement was achieved by the developed NEXT noise cancellation technique.

Larger systems today, like telephone and optical switches, are usually based on a multiboard architecture where a set of printed-circuit boards are connected to a backplane board. These systems are also equipped with Boundary-Scan to enable testing, however, the backplane in a multi-board system has a limited wiring capability, which makes the additional backplane Boundary-Scan wiring highly costly. The problem is to access the Boundary-Scan enabled boards with the Boundary-Scan controller located at a central board. In this MSc. thesis project we propose an approach suitable for the Advanced Telecommunication Computing Architecture (ATCA) standard where we make use of the existing Intelligent Platform Management Bus (IPMB) and expands its protocol for application of Boundary-Scan tests. We have also defined a command set as well as a test data format for storing embedded test data on the boards to support the remote execution of Boundary-Scan tests. For validation of the proposed approach we have developed demonstrator.

Jitter requirements have become more stringent with higher speed serial communication links. Reducing jitter, with the main focus on reducing data dependant jitter (DDJ), is presented by employing adaptive finite impulse response (FIR) filter pre-emphasis. The adaptive FIR pre-emphasis is implemented in the IBM 7WL 0.18 µm SiGe BiCMOS process. SiGe heterojunction bipolar transistors (HBTs) provide high bandwidth, low noise devices which could reduce the total system jitter. The trade-offs between utilising metal oxide semiconductor (MOS) current mode logic (CML) and SiGe bipolar CML are also discussed in comparison with a very high fT (IBM 8HP process with fT = 200 GHz) process. A reduction in total system jitter can be achieved by keeping the sub-components of the system jitter constant while optimising the DDJ. High speed CML circuits have been employed to allow data rates in excess of 5 Gb/s to be transmitted whilst still maintaining an internal voltage swing of at least 300 mV. This allows the final FIR filter adaptation scheme to minimise the DDJ within 12.5 % of a unit interval, at a data rate of 5 Gb/s implementing 6 FIR pre-emphasis filter taps, for a worst case copper backplane channel (30" FR-4 channel). The implemented integrated circuit (IC) designed as part of the verification process takes up less than 1 mm2 of silicon real estate. In this dissertation, SPICE simulation results are presented, as well as the novel IC implementation of the proposed FIR filter adaptation technique as part of the hypothesis verification procedure. The implemented transmitter and receiver were tested for functionality, and showed the successful functional behaviour of all the implemented CML gates associated with the first filter tap. However, due to the slow charge and discharge rate of the pulse generation circuit in both the transmitter and receiver, only the main operational state of the transmitter could be experimentally validated. As a result of the adaptation scheme implemented, the contribution in this research lies in that a designer utilising such an IC can optimise the DDJ, reducing the total system jitter, and hence increasing the data fidelity with minimal effort. / Dissertation (MEng)--University of Pretoria, 2011. / Electrical, Electronic and Computer Engineering / unrestricted