A 4-PAM/2-PAM receiver analog front-end (AFE) targeting 20GSymbol/s for use with coaxial cable channels is presented. Behavioral simulations incorporate a transmitter, scalable coaxial cable model, and the proposed receiver architecture, targeting cable loss of 32dB at 10GHz. To accommodate links of varying lengths, the AFE includes a variable-gain amplifier (VGA) and analog peaking equalizer. The input preamplifier is important for achieving the required input sensitivity. A DC bias current is introduced through the feedback resistor in a conventional shunt-shunt feedback nMOS transimpedance amplifier (TIA) to level-shift the output, obviating a following level-shifting stage. The fabricated AFE occupies 0.89mm2 in a 90-nm CMOS process and dissipates 138mW from a 1.3V supply. The AFE amplifies and opens the eye pattern of a 20-Gb/s 2-PAM data stream transmitted over coaxial cable with 7.5dB loss at 10GHz.

A 4-PAM/2-PAM receiver analog front-end (AFE) targeting 20GSymbol/s for use with coaxial cable channels is presented. Behavioral simulations incorporate a transmitter, scalable coaxial cable model, and the proposed receiver architecture, targeting cable loss of 32dB at 10GHz. To accommodate links of varying lengths, the AFE includes a variable-gain amplifier (VGA) and analog peaking equalizer. The input preamplifier is important for achieving the required input sensitivity. A DC bias current is introduced through the feedback resistor in a conventional shunt-shunt feedback nMOS transimpedance amplifier (TIA) to level-shift the output, obviating a following level-shifting stage. The fabricated AFE occupies 0.89mm2 in a 90-nm CMOS process and dissipates 138mW from a 1.3V supply. The AFE amplifies and opens the eye pattern of a 20-Gb/s 2-PAM data stream transmitted over coaxial cable with 7.5dB loss at 10GHz.

A combined solution of the Feed-Forward Equalizer (FFE) and Near-End Crosstalk (NEXT) noise cancellation technique was suggested. The techniques increase data throughput and improve link quality in the 20-in FR4 legacy backplane application. Backplane channel loss and coupling noise were measured and characterized to develop the corresponding behavioral channel model. The receiver-side FFE with 4-tap Finite Impulse Response (FIR) filter structure was adopted as the optimum equalizer topology. The 4-tap FIR filter consists of tap delay line with tap-spacing 33 ps and linear tap-gain amplifiers. The tap coefficients were calculated with the Minimum-Mean-Squared-Error (MMSE) algorithm. A 0.18-um CMOS 4-tap FIR filter IC was designed and fabricated. The experiment results showed the 20-Gbit/sec 4-PAM and 10-Gbit/sec NRZ signal were successfully equalized for the 20-in FR4 legacy backplane channel. Moreover, the suggested NEXT noise cancellation technique consists of coarse- and fine-cancellation stages. The 0.18-um CMOS building block ICs such as 7-tap FIR filter, tunable active Pole-Zero (PZ) filter, and a temporal alignment delay line were fabricated. The experiment results showed that 6-dB Signal-to-Noise Ratio (SNR) improvement was achieved by the developed NEXT noise cancellation technique.

<p>This thesis presents the design of a broadband and high speed dc-coupled AGC amplifier for multi-level (4-PAM) signaling with a symbol rate of 1-GS/s ( 2-Gb/s ) . It is a high frequency analog design with several design challenges such as high -3 dB bandwidth ( greater than 500 MHz ) and highly linear gain while accommodating a large input swing range ( 120 mVp-p to 1800 mVp-p diff.) and delivering constant</p><p>differential output swing of 1700 mVp-p to 50-ohm off-chip loads at high speed. Moreover, the gain control circuit has been designed in analog domain. The amplifier incorporates both active and passive feedback in shunt-shunt topology in order to achieve wide bandwidth. This standalone chip has been implemented in AMS 0.35 micron CMOS process. The post layout eye-diagrams seem to be quite satisfactory.</p>

This thesis presents the design of a broadband and high speed dc-coupled AGC amplifier for multi-level (4-PAM) signaling with a symbol rate of 1-GS/s ( 2-Gb/s ) . It is a high frequency analog design with several design challenges such as high -3 dB bandwidth ( greater than 500 MHz ) and highly linear gain while accommodating a large input swing range ( 120 mVp-p to 1800 mVp-p diff.) and delivering constant differential output swing of 1700 mVp-p to 50-ohm off-chip loads at high speed. Moreover, the gain control circuit has been designed in analog domain. The amplifier incorporates both active and passive feedback in shunt-shunt topology in order to achieve wide bandwidth. This standalone chip has been implemented in AMS 0.35 micron CMOS process. The post layout eye-diagrams seem to be quite satisfactory.