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  • About
  • The Global ETD Search service is a free service for researchers to find electronic theses and dissertations. This service is provided by the Networked Digital Library of Theses and Dissertations.
    Our metadata is collected from universities around the world. If you manage a university/consortium/country archive and want to be added, details can be found on the NDLTD website.
1

Wideband Amplifier Design for STO Technology

Chen, Tingsu January 2011 (has links)
Spin Torque Oscillator (STO) is a promising technology for microwave and radar applications due to its large tunability, miniature size, high operation frequency, high integration level, etc. However, the technology comes also with issues and challenges,such as low output power and spectrum impurity. For instance, in order to apply the STO technology into communication systems, an amplifier is required to compensate the STO’s low output power.     This thesis presents an amplifier for promising Magnetic Tunnel Junction (MTJ) STO devices. The motional resistance of different MTJ STO devices varies from several Ohms to hundreds Ohms, which makes the design challenging. This thesis focuses first on extracting the amplifier requirements using the state-of-the-art MTJ STO devices. The operation frequency of MTJ STO is in the range of 4-8GHzwith a -40~-60 dBm output power. Therefore, a wideband amplifier with 45-65 dB gain is required. Then based on the amplifier requirements, an amplifier topology is proposed, which is composed of two types of input balun-LNA stages depending onthe motional resistance of the STO, a broadband limiting amplifier and an outputbuffer. CG-CS architecture is suitable for the input balun-LNA in the small motional resistance case and cascoded-CS architecture is suitable for the large motional resistance case. The limiting amplifier and the output buffer are the common circuits shared by two cases via switches.     The wideband amplifier for STO is implemented using a 65nm CMOS process with 1.2 V supply and it exhibits 52.36 dB gain with 1.34-11.8 GHz bandwidth insmall motional resistance case and 59.29 dB gain with 1.171-8.178 GHz bandwidth in large motional resistance case. The simulation results show that the amplifier has very low power consumption and meets the linearity and noise performance requirements.
2

WIDEBAND, HIGH DATA RATE KU-BAND MODULATOR DRIVER AMPLIFIER FOR HIGH RELIABILITY SPACEBORNE APPLICATIONS

Gassmann, Jeremy D. 18 October 2010 (has links)
No description available.
3

Design of a High Speed AGC Amplifier for Multi-level Coding

Bhuiya, Iftekharul Karim January 2006 (has links)
<p>This thesis presents the design of a broadband and high speed dc-coupled AGC amplifier for multi-level (4-PAM) signaling with a symbol rate of 1-GS/s ( 2-Gb/s ) . It is a high frequency analog design with several design challenges such as high -3 dB bandwidth ( greater than 500 MHz ) and highly linear gain while accommodating a large input swing range ( 120 mVp-p to 1800 mVp-p diff.) and delivering constant</p><p>differential output swing of 1700 mVp-p to 50-ohm off-chip loads at high speed. Moreover, the gain control circuit has been designed in analog domain. The amplifier incorporates both active and passive feedback in shunt-shunt topology in order to achieve wide bandwidth. This standalone chip has been implemented in AMS 0.35 micron CMOS process. The post layout eye-diagrams seem to be quite satisfactory.</p>
4

Design of a High Speed AGC Amplifier for Multi-level Coding

Bhuiya, Iftekharul Karim January 2006 (has links)
This thesis presents the design of a broadband and high speed dc-coupled AGC amplifier for multi-level (4-PAM) signaling with a symbol rate of 1-GS/s ( 2-Gb/s ) . It is a high frequency analog design with several design challenges such as high -3 dB bandwidth ( greater than 500 MHz ) and highly linear gain while accommodating a large input swing range ( 120 mVp-p to 1800 mVp-p diff.) and delivering constant differential output swing of 1700 mVp-p to 50-ohm off-chip loads at high speed. Moreover, the gain control circuit has been designed in analog domain. The amplifier incorporates both active and passive feedback in shunt-shunt topology in order to achieve wide bandwidth. This standalone chip has been implemented in AMS 0.35 micron CMOS process. The post layout eye-diagrams seem to be quite satisfactory.
5

CMOS High Frequency Circuits for Spin Torque Oscillator Technology

Chen, Tingsu January 2014 (has links)
Spin torque oscillator (STO) technology has a unique blend of features, including but not limited to octave tunability, GHz operating frequency, and nanoscaled size, which makes it highly suitable for microwave and radar applications. This thesis studies the fundamentals of STOs, utilizes the state-of-art STO's advantages, and proposes two STO-based microwave systems targeting its microwave applications and measurement setup, respectively. First, based on an investigation of possible STO applications, the magnetic tunnel junction (MTJ) STO shows a great suitability for microwave oscillator in multi-standard multi-band radios. Yet, it also imposes a large challenge due to its low output power, which limits it from being used as a microwave oscillator. In this regard, different power enhancement approaches are investigated to achieve an MTJ STO-based microwave oscillator. The only possible approach is to use a dedicated CMOS wideband amplifier to boost the output power of the MTJ STO. The dedicated wideband amplifier, containing a novel Balun-LNA, an amplification stage and an output buffer, is proposed, analyzed, implemented, measured and used to achieve the MTJ STO-based microwave oscillator. The proposed amplifier core consumes 25.44 mW from a 1.2 V power supply and occupies an area of 0.16 mm2 in a 65 nm CMOS process. The measurement results show a S21 of 35 dB, maximum NF of 5 dB, bandwidth of 2 GHz - 7 GHz. This performance, as well as the measurement results of the proposed MTJ STO-based microwave oscillator, show that this microwave oscillator has a highly-tunable range and is able to drive a PLL. The second aspect of this thesis, firstly identifies the major difficulties in measuring the giant magnetoresistance (GMR) STO, and hence studying its dynamic properties. Thereafter, the system architecture of a reliable GMR STO measurement setup, which integrates the GMR STO with a dedicated CMOS high frequency IC to overcome these difficulties in precise characterization of GMR STOs, is proposed. An analysis of integration methods is given and the integration method based on wire bonding is evaluated and employed, as a first integration attempt of STO and CMOS technologies. Moreover, a dedicated high frequency CMOS IC, which is composed of a dedicated on-chip bias-tee, ESD diodes, input and output networks, and an amplification stage for amplifying the weak signal generated by the GMR STO, is proposed, analyzed, developed, implemented and measured. The proposed dedicated high frequency circuits for GMR STO consumes 14.3 mW from a 1.2 V power supply and takes a total area of 0.329 mm2 in a 65 nm CMOS process. The proposed on-chip bias-tee presents a maximum measured S12 of -20 dB and a current handling of about 25 mA. Additionally, the proposed dedicated IC gives a measured gain of 13 dB with a bandwidth of 12.5 GHz - 14.5 GHz. The first attempt to measure the (GMR STO+IC) pair presents no RF signal at the output. The possible cause and other identified issues are given. / <p>QC 20140114</p>

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