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Le développement permanent des applications informatiques telles que le stockage de masse, le calcul intensif et les communications large bande, encourage l’émergence de nouvelles technologies de communication. D’une part, les communications à travers des interconnexions métalliques approchent de leurs limites intrinsèques en termes d’énergie, surface et coût par bit. D’autre part, la photonique hybride conventionnelle, basée sur des assemblages 2D/3D de composants photoniques en technologies III-V, ne peut pas être complètement intégrée. Le développement de nouvelle architecture photonique sur silicium est une bonne alternative afin de proposer des systèmes intégrés de communication haut débit. La conception d’un modulateur électro-optique à très haut débit sur silicium fait l’objet de cette thèse. Dans un premier temps, un état de l’art des différents systèmes optiques est dressé, afin d’identifier les principaux verrous technologiques limitant leurs performances. Suite à l’analyse des différents types de modulateur optique implémentés sur silicium, une proposition d’architecture a été faite pour un modulateur Mach Zehnder 100 Gbits/s. Ce premier circuit a été développé avec la technologie PIC25G du fondeur STMicroelectronics. Le driver de ce modulateur a, quant à lui, été conçu avec la technologie 55 nm SiGe BiCMOS de ce même fondeur. Le démonstrateur proposé dans ces travaux offre un débit de 100 Gbits/s avec une modulation NRZ sur une unique voie optique. Pour cette configuration, ce prototype offre un débit binaire au-delà de l’état de l’art (pour une unique voie de transmission optique) avec une énergie par bit de 80 pJ/bit. / The sustained development of software applications including mass storage, intensive computing and broadband communication, motivates the emergence of novel communication technologies. On one hand, communications through metallic interconnections approach their inherent limitations in term of energy, area and cost per bit. On the other hand, conventional hybrid photonics, based on discrete 2D/3D photonic assemblies of III-V photonic devices, cannot be integrated. The rising silicon photonic technology, thanks to its high level of integration, overcomes the shortcomings of the two previous approaches and promises a low cost solution allowing close proximity integration of photonics with electronics.The design of a very high data rate electro-optic modulator on silicon is reported in this thesis manuscript. In a first section, the state of the art of optic systems is presented with a focus on the main technological challenges limiting performances. Then, a silicon based topology is introduced to achieve a 100 Gbs Mach Zehnder modulator. It was implemented with the STMicroelectronics PIC25G technology. The driver of this modulator was designed with the 55 nm SiGe BiCMOS technology of the same founder. The demonstrator introduced in this work offer a 100 Gbs data rate with an NRZ modulation on a single optical channel. For this configuration, this prototype provides a data rate beyond the state of the art (for a single optical transmission path) with an energy per bit of 80 pJ/bit.

This thesis addresses basic scientific research in the field of transmitter front-end circuits for electro-optical data communication. First, the theoretical fundamentals are presented and analyzed. Based on the theoretical considerations, conceptual circuit designs are studied. Finally, in order to prove the described concepts, the circuits were experimentally characterized and subsequently compared to other works in the literature. The analysis covers key theoretical aspects regarding transmitter front-end circuits. It starts from the basic physical effects inside a transistor and ends with the design of high-swing modulator drivers. Furthermore, it comprises the fundamentals of optical modulators as well as the integration of the electrical driver with the modulator. First, the concept of a basic monolithically integrated transmitter consisting of a Mach-Zehnder modulator (MZM) and an electrical driver is presented. The circuit reaches a bit-error-free data rate of 37 Gb/s, which is a record among other monolithically integrated transmitters reported in the literature. It was shown that by employing a high-swing driver, high extinction ratios (ER) can be achieved (namely 8.4 dB at 25 Gb/s and 7.6 dB at 35 Gb/s) while using short-length phase shifters (2 mm of length). It was therefore proved that one of the main drawbacks of the MZM-based transmitters, namely their large chip area, can be mitigated by using high-swing drivers, however without sacrificing the ER. Next, an improved modulator driver design is investigated, the focus of the study being the linearity. In addition to a high peak-to-peak differential output voltage swing of 7.2 Vpp,d, the driver achieves record-low total harmonic distortion (THD) values of 1% (at 1 GHz, for the output swing of 6.5 Vpp,d) and 1.7% (at 1 GHz, for the output swing of 7 Vpp,d). Moreover, the driver reaches a bandwidth of 61.2 GHz and shows a high power efficiency when relating its DC power consumption to its output voltage swing. The achievement of a high linearity and bandwidth without an increased power consumption is due to the fact that the bias currents of the emitter-follower (EF) stages are provided by means of resistors instead of the conventional current sources. The two approaches were first analyzed mathematically and subsequently compared by means of circuit simulations. It was shown that the proposed approach for the realization of the EFs – i.e. by means of resistors – allows a reduction of the DC power consumption by 19% compared to the current-source approach for an equivalent performance in terms of linearity and bandwidth. Finally, a modulator driver concept suitable for higher-order modulation formats is studied, namely the 8-level pulse amplitude modulation (PAM-8). The circuit was realized as a 3-bit digital-to-analog converter (DAC), thus being able to yield 8-level output signals. Moreover, the circuit is able to function as a PAM-4 driver as well, thanks to the tunable tail currents of the DAC core. It achieves a symbol rate of 50 Gbaud, which corresponds to a bit rate of 150 Gb/s for the PAM-8 modulation and 100 Gb/s for PAM-4. The study showed that a modulator driver can be realized that is able to switch between different modulation formats (namely PAM-8 and PAM-4), without requiring extra power or additional circuit parts. Moreover, the use of on-chip single-to-differential converters (SDCs) targets the relaxation of the requirements on the stages that precede the driver. Finally, relating its DC power consumption (590 mW, including the SDCs) to its output voltage swing (4 Vpp,d), the driver shows one of the highest power efficiencies among PAM modulator drivers in the literature.