The internet revolution has led to the demand for high speed, low cost solutions for providing high bandwidth to the consumers. Cable and DSL systems address these requirements through sophisticated analog and digital signal processing schemes. A key element of the analog front end of such systems is the line driver which interfaces with the transmission medium such as co-axial cable or twisted pair. The line driver is an amplifier that provides the necessary output current to drive the low impedance of the line. The main requirements for design are high output swing, high linearity, matched impedance to the line and power efficiency. These requirements are addressed by a class AB amplifier whose output impedance can be controlled through feedback. The property of this topology is that when the gain is unity, the output resistance of the driver is matched to the line resistance. Unity gain is achieved for varying line conditions through a tuning loop consisting of peak-to-peak detectors and differential difference amplifier. The design is fabricated in 0.5 micron AMI CMOS process technology. For line variations from 65 to 170 ohms, the gain is unity with an error of 3 % and the impedance matching error is 20 % at the worst-case. The linearity is better than 50 dB for a 1.2 V peak-to-peak signal over the signal bandwidth from 10 kHz to 5 MHz and the line resitance range from 65 to 160 ohms.

<p>This thesis presents the design of a broadband and high speed dc-coupled AGC amplifier for multi-level (4-PAM) signaling with a symbol rate of 1-GS/s ( 2-Gb/s ) . It is a high frequency analog design with several design challenges such as high -3 dB bandwidth ( greater than 500 MHz ) and highly linear gain while accommodating a large input swing range ( 120 mVp-p to 1800 mVp-p diff.) and delivering constant</p><p>differential output swing of 1700 mVp-p to 50-ohm off-chip loads at high speed. Moreover, the gain control circuit has been designed in analog domain. The amplifier incorporates both active and passive feedback in shunt-shunt topology in order to achieve wide bandwidth. This standalone chip has been implemented in AMS 0.35 micron CMOS process. The post layout eye-diagrams seem to be quite satisfactory.</p>

This thesis presents the design of a broadband and high speed dc-coupled AGC amplifier for multi-level (4-PAM) signaling with a symbol rate of 1-GS/s ( 2-Gb/s ) . It is a high frequency analog design with several design challenges such as high -3 dB bandwidth ( greater than 500 MHz ) and highly linear gain while accommodating a large input swing range ( 120 mVp-p to 1800 mVp-p diff.) and delivering constant differential output swing of 1700 mVp-p to 50-ohm off-chip loads at high speed. Moreover, the gain control circuit has been designed in analog domain. The amplifier incorporates both active and passive feedback in shunt-shunt topology in order to achieve wide bandwidth. This standalone chip has been implemented in AMS 0.35 micron CMOS process. The post layout eye-diagrams seem to be quite satisfactory.