In this work, the design of a CMOS broadband low noise amplifier with inherent high performance single-to-differential conversion is presented. These characteristics are driven by the double quadrature single conversion digital television tuner which requires accurately balanced differential signals to perform its function and to improve image rejection. A three-stage amplifier is designed to satisfy several requirements of front-end circuits at the same time. The resistive shunt-feedback topology is adopted to implement a single-ended broadband low-noise amplifier as the first stage. The second stage is an on-chip single-to-differential converter, which employs a novel method to improve its balancing performance. A fully differential buffer capable of driving heavy loads is used as the third stage to further suppress the phase and magnitude errors of output differential signals. Fabricated in 0.35??m TSMC standard CMOS technology, the designed broadband front-end amplifier manages to limit the phase error to within ??1.5?? and magnitude error ??0.75dB over 50~850 MHz frequency range, with 16dB gain and a noise figure of 4dB.

In this thesis work, a 3-stage ultra broadband amplifier operating in 2-18 GHz frequency band with gain 23 dB is designed, simulated and fabricated. The amplifier is based on cascaded, reactively terminated single stage distributed amplifier (CRTSSDA) concept. The idea of including reactive terminations to achieve broadband gain is investigasted and simulated. The simulated design is fabricated and measurements of the fabricated amplifier are compared with simulation results. Also practical experience on working at high frequencies with surface mount components is presented in this thesis work.

In this thesis work, a new distributed amplifier topology is discussed and applied to three different cases. The topology is based on dividing the frequency spectrum into channels and amplifying afterwards. The channelized and amplified signals are then combined at the output for broadband amplification. This topology is used in the design of a three channel 0.1-1 GHz amplifier with a gain of 14.5&plusmn / 0.6 dB. The design is fabricated, and then the measured and simulated results are compared. A second 0.1-1 GHz amplifier with 21&plusmn / 1 dB is designed in simulation environment with five channels. This five channel amplifier is fabricated and measured results are compared with the simulated ones. A 1-6 GHz three channel amplifier is also designed with a gain of 10.5&plusmn / 0.5 dB. Application of the proposed topology to three different designs shows promising results for future amplifier designs.

<p>This thesis presents the design of a broadband and high speed dc-coupled AGC amplifier for multi-level (4-PAM) signaling with a symbol rate of 1-GS/s ( 2-Gb/s ) . It is a high frequency analog design with several design challenges such as high -3 dB bandwidth ( greater than 500 MHz ) and highly linear gain while accommodating a large input swing range ( 120 mVp-p to 1800 mVp-p diff.) and delivering constant</p><p>differential output swing of 1700 mVp-p to 50-ohm off-chip loads at high speed. Moreover, the gain control circuit has been designed in analog domain. The amplifier incorporates both active and passive feedback in shunt-shunt topology in order to achieve wide bandwidth. This standalone chip has been implemented in AMS 0.35 micron CMOS process. The post layout eye-diagrams seem to be quite satisfactory.</p>

This thesis presents the design of a broadband and high speed dc-coupled AGC amplifier for multi-level (4-PAM) signaling with a symbol rate of 1-GS/s ( 2-Gb/s ) . It is a high frequency analog design with several design challenges such as high -3 dB bandwidth ( greater than 500 MHz ) and highly linear gain while accommodating a large input swing range ( 120 mVp-p to 1800 mVp-p diff.) and delivering constant differential output swing of 1700 mVp-p to 50-ohm off-chip loads at high speed. Moreover, the gain control circuit has been designed in analog domain. The amplifier incorporates both active and passive feedback in shunt-shunt topology in order to achieve wide bandwidth. This standalone chip has been implemented in AMS 0.35 micron CMOS process. The post layout eye-diagrams seem to be quite satisfactory.

Ces travaux de recherche visent à introduire et à généraliser l'utilisation des systèmes différentiels dans les applications RF et Micro-ondes. En particulier, dans la conception de dispositifs pour les fonctions d'amplification à faible bruit. Pour cela, il est indispensable de développer des outils fiables et rigoureux tels que le formalisme des modes mixtes introduit par Bockelman. C'est dans cet esprit que s'inscrit la première phase de l'étude. Le but étant de développer un outil pour l'analyse de la stabilité linéaire des systèmes différentiels à trois et quatre accès. Par ailleurs, les interfaces des circuits numériques ultra-rapides (CNA) sont de topologie différentielle. Ce qui augmente encore l'intérêt de disposer de méthodes rigoureuses pour la conception des systèmes différentiels. Dans la deuxième phase de l'étude la problématique de l'intégration système des CNAs dans les nouvelles générations des chaines de transmission RF des satellites de télécommunications est traitée. La conception d'un balun actif large bande capable d'assurer la conversion de la sortie analogique différentielle du CNA en sortie simple accès (Single-ended) référencée par rapport à la masse est détaillée. Afin de répondre aux contraintes d'intégration, une technologie BiCMOS SiGe 0.25 μm est utilisée pour son implémentation. Les performances obtenues par la mesure de la puce Silicium réalisée respectent les spécifications techniques initiales de l'application. Ce qui permet de valider la méthodologie de conception utilisée. L'objectif final est d'être capable d'intégrer sur un même substrat monolithique le CNA et le balun actif large bande de conversion de modes. / This research work aims to develop analytical tools for the analysis and design of differential systems. While the use of differential circuits in RF reception/transmission chains is increasingly growing, there is no accurate method to study their stability. First the common tools to study RF differential components are introduced. Then, the development of a CAD tool that can be rigorously used to investigate the extrinsic stability of linear differential systems is presented. Finally this tool is applied to study the stability of in a real case. The design addresses a three port component that aims to convert the differential output of digital to analog converter into a single-ended access for a spatial application purpose. This broadband active balun is designed using BiCMOS technology. Measurements are performed and the results are in good agreement with the simulation. All the initial specications are achieved, which validate the approach developed in this study.

Optimizing a modulator driver for linear and high-speed operation, while simultaneously achieving a high output voltage swing is very challenging. This paper investigates the design of a highlylinear, high-bandwidth yet power-efficient Mach-Zehnder modulator driver based on the breakdown voltage doubler concept, which overcomes the transistors' physical limitations and enables output voltage swings twice as high as conventional differential pair amplifiers can provide. The low-power design was enabled by the use of an open-collector topology for the output stage as well as by employing resistors instead of current mirrors in order to provide the bias currents for the emitter-follower (EF) stages. We show that by means of this EF implementation approach, the power consumption can be reduced by 19% without sacrificing the circuit's bandwidth and linearity. The driver achieves peak-to-peak differential output voltage swings above 6.5 Vpp,d and consumes 670mWof DC power, being one of the most power-efficient drivers in the literature. The 3-dB bandwidth is 61.2 GHz and the total harmonic distortion is 1%, measured at 1 GHz and for the output swing of 6.5 Vpp,d. To the best of the authors' knowledge, these are the highest linearity and output voltage swing reported in the literature for modulator drivers with bandwidths above 40 GHz.