<p>Larger systems today, like telephone and optical switches, are usually based on a multiboard architecture where a set of printed-circuit boards are connected to a backplane board. These systems are also equipped with Boundary-Scan to enable testing, however, the backplane in a multi-board system has a limited wiring capability, which makes the additional backplane Boundary-Scan wiring highly costly. The problem is to access the Boundary-Scan enabled boards with the Boundary-Scan controller located at a central board. In this MSc. thesis project we propose an approach suitable for the Advanced Telecommunication Computing Architecture (ATCA) standard where we make use of the existing Intelligent Platform Management Bus (IPMB) and expands its protocol for application of Boundary-Scan tests. We have also defined a command set as well as a test data format for storing embedded test data on the boards to support the remote execution of Boundary-Scan tests. For validation of the proposed approach we have developed demonstrator.</p>

[pt] Os ensaios dielétricos em equipamentos para alta tensão em corrente alternada (ATCA) e corrente contínua (ATCC) requerem medições de grandezas elétricas, e as análises de desempenho dos equipamentos ensaiados são diretamente dependentes dos resultados obtidos por tais medições. Atualmente, para garantir a confiabilidade dos resultados dos ensaios, é necessário que a forma de onda da tensão aplicada ao equipamento esteja dentro dos níveis de distorção exigidos por norma. Para que ensaios possam ser realizados de forma normalizada, todos os parâmetros descritos na norma ABNT NBR IEC 60060-1:2013 devem ser monitorados durante os ensaios em ATCA e ATCC. Normalmente um Sistema de Medição para Alta Tensão (SMAT) é formado por um divisor de tensão, um cabo de transmissão e um multímetro de bancada, permitindo assim uma análise quantitativa da tensão de ensaio por meio da medição do valor eficaz e/ou do valor médio. Entretanto, esse SMAT é inadequado para o monitoramento de todos os parâmetros normalizados, restringindo sua aplicação a uma análise puramente quantitativa da tensão de ensaio. Deste modo, o objetivo desta dissertação foi o desenvolvimento e validação de algoritmos de medição que fossem capazes de estimar todos os parâmetros normalizados. Sua validação foi realizada mediante ensaios experimentais em alta e baixa tensão, assim como pelo processamento das formas de onda digitais padrão pertencentes ao rascunho da norma IEC 61083-4. Os resultados obtidos foram positivos e dentro de limites aceitáveis, possibilitando a implantação desses algoritmos de medição nos laboratórios de ensaios (AT1, AT2, AT3, LabUAT) do CEPEL. / [en] Dielectric tests on equipment with high voltage alternating current (HVAC) and direct current (HVDC) require measurements of electrical quantities, and the performance analysis of the tested equipment is directly dependent on the results obtained by those measurements. Currently, to ensure the reliability of the test results, the voltage waveforms applied to the equipment must be within the distortion levels required by standard. For tests to be performed in a standardized way, all parameters described in ABNT NBR IEC 60060-1: 2013 must be monitored during the HVAC and HVDC tests. Normally, a High Voltage Measurement System is formed by a voltage divider, a transmission cable and a multimeter, allowing a quantitative analysis of the test voltage by measuring the RMS value and/or mean value. However, this High Voltage Measurement System is inadequate for the monitoring all standard parameters, restricting its application to a purely quantitative analysis of the test voltage. Therefore, the objective of this dissertation was the development and validation of measurement algorithms that are able to estimate all the normalized parameters. Its validation was carried out through experimental tests in high and low voltage, as well as by the processing of the standard digital waveforms belonging to the draft of the standard IEC 61083-4. The results were positive and within acceptable limits, allowing the implementation of these measurement algorithms in CEPEL test (AT1, AT2, AT3, LabUAT) laboratories.

Larger systems today, like telephone and optical switches, are usually based on a multiboard architecture where a set of printed-circuit boards are connected to a backplane board. These systems are also equipped with Boundary-Scan to enable testing, however, the backplane in a multi-board system has a limited wiring capability, which makes the additional backplane Boundary-Scan wiring highly costly. The problem is to access the Boundary-Scan enabled boards with the Boundary-Scan controller located at a central board. In this MSc. thesis project we propose an approach suitable for the Advanced Telecommunication Computing Architecture (ATCA) standard where we make use of the existing Intelligent Platform Management Bus (IPMB) and expands its protocol for application of Boundary-Scan tests. We have also defined a command set as well as a test data format for storing embedded test data on the boards to support the remote execution of Boundary-Scan tests. For validation of the proposed approach we have developed demonstrator.

Submitted by LUCAS ARRUDA RAMALHO null (lucasarrudaramalho@gmail.com) on 2018-03-14T22:14:34Z No. of bitstreams: 1 Ramalho_Tese_2018.pdf: 8417019 bytes, checksum: 0b39588579fa6ac3abad291909bc4662 (MD5) / Approved for entry into archive by Cristina Alexandra de Godoy null (cristina@adm.feis.unesp.br) on 2018-03-15T14:45:53Z (GMT) No. of bitstreams: 1 ramalho_la_dr_ilha.pdf: 8417019 bytes, checksum: 0b39588579fa6ac3abad291909bc4662 (MD5) / Made available in DSpace on 2018-03-15T14:45:53Z (GMT). No. of bitstreams: 1 ramalho_la_dr_ilha.pdf: 8417019 bytes, checksum: 0b39588579fa6ac3abad291909bc4662 (MD5) Previous issue date: 2018-02-23 / Coordenação de Aperfeiçoamento de Pessoal de Nível Superior (CAPES) / A evolução dos Multi Gigabit Transceivers (MGT) nos Field Programmable Gate Arrays (FPGA) trouxeram oportunidades para o desenvolvimento de sistemas de aquisição e formatadores de dados em diversas áreas. As novas famílias de FPGAs são capazes de lidar com canais de transmissão com velocidade da ordem de Gbps que utilizam protocolos seriais de alta velocidade, podendo assim se tornar o futuro dos processadores downstream ou upstream. Os sistemas digitais criados para esse propósito, precisam ser confiáveis e síncronos entre dezenas de canais e placas. Como forma de permitir o teste de projetos com essa taxa massiva de bits, essa tese descreve o desenvolvimento do Data Sourcing System (DSS). Esse sistema deve ser capaz de testar qualquer application upstream ou downstream, permitir controle e acesso remoto aos sinais internos dos FPGAs, medir sincronismo e latência entre MGTs e avaliar integridade de links através de bit error rate (BER). Este trabalho faz parte de uma colaboração internacional liderada pelo Fermilab que propôs, com a contribuição do sistema descrito nesta tese, um sistema de trigger de nível 1 para o Compact Muon Solenoid (CMS) Outer Tracker. O dectetor CMS é um experimento vinculado ao European Organization for Nuclear Research (CERN). O DSS foi implementado sobre a placa Pulsar 2b, uma placa padrão Advanced Telecommunication Computing Architecture (ATCA), desenvolvida pelo Fermilab, que conta com um dispositivo FPGA para programação e costumização de aplicações. O setup de hardware utilizado foi construído sobre dois bastidores ATCA com 12 placas Pulsares 2b em cada. A taxa de dados máxima atingida foi de 3.84 Tbps entre os dois bastidores ATCAs. O DSS está operacional e foi utilizado para emular o fluxo de dados de saída do CMS Silicon Outer Tracker, e auxiliar na demonstração da proposta trigger de nível 1. Esta tese descreve essa demonstração como estudo de caso, que testa o formatador de dados do trigger (downstream) através do DSS e- mulando a saída de dados do detector. Nesse estudo de caso, tanto o DSS e o trigger proposto foram implementados utilizando o mesmo hardware ATCA e a Pulsar 2b. O foco do estudo de caso é descrever a comunicação entre o Data Sourcing shelf e o Pattern Recognition shelf. O DSS atendeu aos requisitos da demonstração provendo uma interface de usuário que permite aos desenvolvedores de trigger inserir sinais de controle e executar operações de leitura e escrita de forma remota nos FPGAs. / The evolution of Fiel Programmable Gate Array (FPGA) Multi Gigabit Transceivers (MGT) brought opportunities for data formatter and data acquisition projects in several areas. The newer FPGA families are capable of handling Gigabits per second (Gbps) I/Os implemented using high speed serial link protocols and to become the future downstream processors. The digital systems created for that purpose need to be reliable and synchronous between dozens of channels and boards. To allow the test of such massive bitrate projects, this work implemented the Data Sourcing System (DSS) e- mulator that is able to produce synchronized data in 12 boards, 480 channels, delivering up to 8 Gbps for each of them. This work is part of a international collaboration, led by Fermilab, that proposed with the contribuition of the system described in this thesis, a Level 1 (L1) tri- gger for the Compact Muon Solenoid (CMS) Outer Tracker. The CMS detector is an European Organization for Nuclear Research (CERN) experiment. The DSS is based on the Pulsar 2b, a custom Advanced Telecommunication Computing Architecture (ATCA) standard FPGA-based board designed by Fermilab to be a scalable high speed link processor system. This hardware setup was implemented at Fermilab using two interconnected ATCA shelves with 12 Pulsar 2b on both. The results show that the system is able to provide data at 3.8 Terabits per second (Tbps), and to measure synchronization, latency and bit error rate of the MGTs. The system is operational and was already used to emulate the CMS Silicon Tracker data, and helped the demonstration of a L1 Trigger approach. This thesis describes the demonstration performed as case of study, which used the DSS as upstream system and tested the trigger data delivery as a downstream. In the case of study, both DSS and the proposed trigger are performed by the same ATCA hardware and the Pulsar 2b. The case of study focused to describe the communication between the Data Sourcing shelf and the Pattern Recognition shelf. Data Sourcing reached those requirements for the demonstration and provided a user interface that allows the trigger developers to insert control signals or to perform W/R operations inside Pulsar 2b FPGA block memories.

Orientador: Aílton Akira Shinoda / Resumo: A evolução dos Multi Gigabit Transceivers (MGT) nos Field Programmable Gate Arrays (FPGA) trouxeram oportunidades para o desenvolvimento de sistemas de aquisição e formatadores de dados em diversas áreas. As novas famílias de FPGAs são capazes de lidar com canais de transmissão com velocidade da ordem de Gbps que utilizam protocolos seriais de alta velocidade, podendo assim se tornar o futuro dos processadores downstream ou upstream. Os sistemas digitais criados para esse propósito, precisam ser confiáveis e síncronos entre dezenas de canais e placas. Como forma de permitir o teste de projetos com essa taxa massiva de bits, essa tese descreve o desenvolvimento do Data Sourcing System (DSS). Esse sistema deve ser capaz de testar qualquer application upstream ou downstream, permitir controle e acesso remoto aos sinais internos dos FPGAs, medir sincronismo e latência entre MGTs e avaliar integridade de links através de bit error rate (BER). Este trabalho faz parte de uma colaboração internacional liderada pelo Fermilab que propôs, com a contribuição do sistema descrito nesta tese, um sistema de trigger de nível 1 para o Compact Muon Solenoid (CMS) Outer Tracker. O dectetor CMS é um experimento vinculado ao European Organization for Nuclear Research (CERN). O DSS foi implementado sobre a placa Pulsar 2b, uma placa padrão Advanced Telecommunication Computing Architecture (ATCA), desenvolvida pelo Fermilab, que conta com um dispositivo FPGA para programação e costumização de aplica... (Resumo completo, clicar acesso eletrônico abaixo) / Abstract: The evolution of Fiel Programmable Gate Array (FPGA) Multi Gigabit Transceivers (MGT) brought opportunities for data formatter and data acquisition projects in several areas. The newer FPGA families are capable of handling Gigabits per second (Gbps) I/Os implemented using high speed serial link protocols and to become the future downstream processors. The digital systems created for that purpose need to be reliable and synchronous between dozens of channels and boards. To allow the test of such massive bitrate projects, this work implemented the Data Sourcing System (DSS) e- mulator that is able to produce synchronized data in 12 boards, 480 channels, delivering up to 8 Gbps for each of them. This work is part of a international collaboration, led by Fermilab, that proposed with the contribuition of the system described in this thesis, a Level 1 (L1) tri- gger for the Compact Muon Solenoid (CMS) Outer Tracker. The CMS detector is an European Organization for Nuclear Research (CERN) experiment. The DSS is based on the Pulsar 2b, a custom Advanced Telecommunication Computing Architecture (ATCA) standard FPGA-based board designed by Fermilab to be a scalable high speed link processor system. This hardware setup was implemented at Fermilab using two interconnected ATCA shelves with 12 Pulsar 2b on both. The results show that the system is able to provide data at 3.8 Terabits per second (Tbps), and to measure synchronization, latency and bit error rate of the MGTs. The system is o... (Complete abstract click electronic access below) / Doutor