<p>Larger systems today, like telephone and optical switches, are usually based on a multiboard architecture where a set of printed-circuit boards are connected to a backplane board. These systems are also equipped with Boundary-Scan to enable testing, however, the backplane in a multi-board system has a limited wiring capability, which makes the additional backplane Boundary-Scan wiring highly costly. The problem is to access the Boundary-Scan enabled boards with the Boundary-Scan controller located at a central board. In this MSc. thesis project we propose an approach suitable for the Advanced Telecommunication Computing Architecture (ATCA) standard where we make use of the existing Intelligent Platform Management Bus (IPMB) and expands its protocol for application of Boundary-Scan tests. We have also defined a command set as well as a test data format for storing embedded test data on the boards to support the remote execution of Boundary-Scan tests. For validation of the proposed approach we have developed demonstrator.</p>

Larger systems today, like telephone and optical switches, are usually based on a multiboard architecture where a set of printed-circuit boards are connected to a backplane board. These systems are also equipped with Boundary-Scan to enable testing, however, the backplane in a multi-board system has a limited wiring capability, which makes the additional backplane Boundary-Scan wiring highly costly. The problem is to access the Boundary-Scan enabled boards with the Boundary-Scan controller located at a central board. In this MSc. thesis project we propose an approach suitable for the Advanced Telecommunication Computing Architecture (ATCA) standard where we make use of the existing Intelligent Platform Management Bus (IPMB) and expands its protocol for application of Boundary-Scan tests. We have also defined a command set as well as a test data format for storing embedded test data on the boards to support the remote execution of Boundary-Scan tests. For validation of the proposed approach we have developed demonstrator.

Le test de circuits analogiques et mixtes est de plus en plus difficile du fait de l’intégration d’un nombre croissant de composants complexes au sein d’un même système. Les techniques de BIST permettent la réalisation d’un test efficace en intégrant au système les ressources nécessaires au test. Dans cette thèse, nous présentons une structure BIST pour les Convertisseurs Analogiques-Numériques (CAN) tout numérique. Le générateur de stimuli est un oscillateur Sigma-Delta numérique délivrant, après un simple filtrage analogique, une sinusoïde. L’analyse de la réponse se fait au moyen d’un banc de filtres numériques séparant les différentes composantes harmoniques du signal issu du CAN. A partir de ces composantes harmoniques, différents paramètres spectraux sont calculés. Afin de valider cette structure, différents prototypes ont été conçu sur FPGA. Les résultats expérimentaux confirment la capacité de notre structure à tester efficacement un CAN 12 bits ayant un SNR de 70 dB. / Analog and mixed circuit testing is more and more difficult because of the integration of agrowing number of complex components in one system. BIST techniques allow the realizationof an effective test system by integrating the test resources to the system. In this thesis, wepresent a BIST Structure for Analog to Digital Converters (ADC). The stimuli generatoris a digital Sigma-Delta oscillator delivering a sine wave after a simple analog filtering. Abank of digital filters separating the different harmonic components of the signal from theADC is used to analyze of the response. From these harmonic components, different spectralparameters are calculated. To validate this structure, different prototypes have been designedon FPGA. The experimental results confirm the ability of our structure to effectively test a12-bit ADC with a 70-dB-SNR.

Organizations gather enormous amounts of data and analyze these data to extract insights that can be useful for them and help them to make better decisions. Predictive data analytics is a crucial subfield within data analytics that make accurate predictions. Predictive data analytics extracts insights from data by using machine learning algorithms. This thesis presents the supervised learning algorithm to perform predicative data analytics in Embedded Test System at the Nordic Engineering Partner company. Predictive Maintenance is a concept that is often used in manufacturing industries which refers to predicting asset failures before they occur. The machine learning algorithms used in this thesis are support vector machines, multi-layer perceptrons, random forests, and gradient boosting. Both binary and multi-class classifier have been provided to fit the models, and cross-validation, sampling techniques, and a confusion matrix have been provided to accurately measure their performance. In addition to accuracy, recall, precision, f1, kappa, mcc, and roc auc measurements are used as well. The prediction models that are fitted achieve high accuracy.

L’émergence des circuits complexes numériques, ou System-On-Chip (SOC), pose notamment la problématique de la consommation énergétique. Parmi les blocs fonctionnels significatifs à ce titre, apparaissent les mémoires et en particulier les mémoires statiques (SRAM). La maîtrise de la consommation énergétique d’une mémoire SRAM inclue la capacité à rendre la mémoire fonctionnelle sous très faible tension d’alimentation, avec un objectif agressif de 300 mV (inférieur à la tension de seuil des transistors standard CMOS). Dans ce contexte, les travaux de thèse ont concerné la proposition d’un point mémoire SRAM suffisamment performant sous très faible tension d’alimentation et pour les nœuds technologiques avancés (CMOS bulk 28nm et FDSOI 28nm). Une analyse comparative des architectures proposées dans l’état de l’art a permis d’élaborer deux points mémoire à 10 transistors avec de très faibles impacts de courant de fuite. Outre une segmentation des ports de lecture, les propositions reposent sur l’utilisation de périphéries adaptées synchrones avec notamment une solution nouvelle de réplication, un amplificateur de lecture de données en mode tension et l’utilisation d’une polarisation dynamique arrière du caisson SOI (Body Bias). Des validations expérimentales s’appuient sur des circuits en technologies avancées. Enfin, une mémoire complète de 32kb (1024x32) a été soumise à fabrication en 28 FDSOI. Ce circuit embarque une solution de test (BIST) capable de fonctionner sous 300mV d’alimentation. Après une introduction générale, le 2ème chapitre du manuscrit décrit l’état de l’art. Le chapitre 3 présente les nouveaux points mémoire. Le 4ème chapitre décrit l’amplificateur de lecture avec la solution de réplication. Le chapitre 5 présente l’architecture d’une mémoire ultra basse tension ainsi que le circuit de test embarqué. Les travaux ont donné lieu au dépôt de 4 propositions de brevet, deux conférences internationales, un article de journal international est accepté et un autre vient d’être soumis. / Emergence of large Systems-On-Chip introduces the challenge of power management. Of the various embedded blocks, static random access memories (SRAM) constitute the angrier contributors to power consumption. Scaling down the power supply is one way to act positively on power consumption. One aggressive target is to enable the operation of SRAMs at Ultra-Low-Voltage, i.e. as low as 300 mV (lower than the threshold voltage of standard CMOS transistors). The present work concerned the proposal of SRAM bitcells able to operate at ULV and for advanced technology nodes (either CMOS bulk 28 nm or FDSOI 28 nm). The benchmarking of published architectures as state-of-the-art has led to propose two flavors of 10-transitor bitcells, solving the limitations due to leakage current and parasitic power consumption. Segmented read-ports have been used along with the required synchronous peripheral circuitry including original replica assistance, a dedicated unbalanced sense amplifier for ULV operation and dynamic forward back-biasing of SOI boxes. Experimental test chips are provided in previously mentioned technologies. A complete memory cut of 32 kbits (1024x32) has been designed with an embedded BIST block, able to operate at ULV. After a general introduction, the manuscript proposes the state-of-the-art in chapter two. The new 10T bitcells are presented in chapter 3. The sense amplifier along with the replica assistance is the core of chapter 4. The memory cut in FDSOI 28 nm is detailed in chapter 5. Results of the PhD have been disseminated with 4 patent proposals, 2 papers in international conferences, a first paper accepted in an international journal and a second but only submitted paper in an international journal.