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  • About
  • The Global ETD Search service is a free service for researchers to find electronic theses and dissertations. This service is provided by the Networked Digital Library of Theses and Dissertations.
    Our metadata is collected from universities around the world. If you manage a university/consortium/country archive and want to be added, details can be found on the NDLTD website.
1

RTL implementation of Viterbi Decoder

Chen, Wei January 2006 (has links)
<p>A forward error correction technique known as convolutional coding with Viterbi decoding was explored in this final thesis. This Viterbi project is part of the baseband Error control project at electrical engineering department, Linköping University.</p><p>In this project, the basic Viterbi decoder behavior model was built and simulated. The convolutional encoder, puncturing, 3 bit soft decision, BPSK and AWGN channel were implemented in MATLAB code. The BER was tested to evaluate the decoding performance.</p><p>The main issue of this thesis is to implement the RTL level model of Viterbi decoder. With the testing results of behavior model, with minimizing the data path, register size and butterflies in the design, we try to achieve a low silicon cost design. The RTL Viterbi decoder model includes the Branch Metric block, the Add-Compare-Select block, the trace-back block, the decoding block and next state block. With all done, we further understand about the Viterbi decoding algorithm and the DSP implementation methods.</p>
2

RTL implementation of Viterbi Decoder

Chen, Wei January 2006 (has links)
A forward error correction technique known as convolutional coding with Viterbi decoding was explored in this final thesis. This Viterbi project is part of the baseband Error control project at electrical engineering department, Linköping University. In this project, the basic Viterbi decoder behavior model was built and simulated. The convolutional encoder, puncturing, 3 bit soft decision, BPSK and AWGN channel were implemented in MATLAB code. The BER was tested to evaluate the decoding performance. The main issue of this thesis is to implement the RTL level model of Viterbi decoder. With the testing results of behavior model, with minimizing the data path, register size and butterflies in the design, we try to achieve a low silicon cost design. The RTL Viterbi decoder model includes the Branch Metric block, the Add-Compare-Select block, the trace-back block, the decoding block and next state block. With all done, we further understand about the Viterbi decoding algorithm and the DSP implementation methods.

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