In recent years, the worldwide progress of wireless communication technology has bringing great benefit and convenience to our people¡¦s life. Nowadays, people can use appliances of wireless communication in many fields, such as family-monitoring, automatic system, and smart-type device¡Ketc. However, in order to dealing with the need of low cost and low power communication, the researcher spend many years on developing the specification of IEEE 802.15.4 Low Rate-Wireless Personal Area Network (LR-WPAN) expected be applied in widespread use. In this thesis, we focus on the baseband signal processing for the physical layer specification of the 868/915MHz mode of the IEEE 802.15.4 LR-WPAN. Our design blocks include packet detection, sampling point detection (energy detection), carrier frequency offset (CFO) compensation, carrier phase offset (CPO) compensation, and despreading algorithms. During the process of simulation, we¡¦ll examine whether our design match the criteria of standard such as sensitivity, packet format, and modulation. While our designs achieve the requirement of the standard, we start on quantization. Finally, we¡¦ll realize the algorithm in VHDL and examine it.

The thesis is mainly in algorithm design and implementation of hardware circuit of baseband signal processing at the transceiver of 2450 MHz band chirp spread spectrum in IEEE 802.15.4a ¡V 2007 Low Rate-Wireless Personal Area Network (LR-WPAN). Due to the characteristic of LR-WPAN such as low cost, low power consumption, small size and easy to implementation, we have to take the complexity and the system performance into consideration. In this thesis, we study on the algorithm design of baseband signal, and analysis the simulation result. At the transmitter, following the specification and realize it. At the receiver, designing the algorithm including the packet detection, energy detection and down-sampling, carrier frequency offset estimation and compensation, timing synchronization, and bi-orthogonal demapper. The system performance after quantizing is 3dB better than the receiver sensitivity we expected. After finishing the algorithm design of the transceiver, we implement the baseband signal circuit by using Verilog Code. Finally, we make an application to National Chip Implementation Center (CIC), and will measure the circuit after the chip tape out. The circuit is fabricated in a 0.18-£gm CMOS technology.

The International Technology Roadmap for Semiconductors projects that embedded memories will occupy increasing System-on-Chip area. The growing density of integration increases the likelihood of fabrication faults. The proposed memory repair strategy employs forward error correction at the system level and mitigates the impact of memory faults through permutation of high sensitivity regions. The effectiveness of the proposed repair technique is demonstrated on a 19.4-Mbit de-interleaver SRAM memory of an ISDB-T digital baseband OFDM receiver in 65-nm CMOS. The proposed technique introduces a single multiplexer delay overhead and a configurable area overhead of M/i bits, where M is the number of memory rows and i is an integer from 1 to M, inclusive. The proposed strategy achieves a measured 0.15 dB gain improvement at a 2e-4 Quasi-Error-Free (QEF) BER in the presence of memory faults for an AWGN channel.

The International Technology Roadmap for Semiconductors projects that embedded memories will occupy increasing System-on-Chip area. The growing density of integration increases the likelihood of fabrication faults. The proposed memory repair strategy employs forward error correction at the system level and mitigates the impact of memory faults through permutation of high sensitivity regions. The effectiveness of the proposed repair technique is demonstrated on a 19.4-Mbit de-interleaver SRAM memory of an ISDB-T digital baseband OFDM receiver in 65-nm CMOS. The proposed technique introduces a single multiplexer delay overhead and a configurable area overhead of M/i bits, where M is the number of memory rows and i is an integer from 1 to M, inclusive. The proposed strategy achieves a measured 0.15 dB gain improvement at a 2e-4 Quasi-Error-Free (QEF) BER in the presence of memory faults for an AWGN channel.

In recent years, the requirement of application such as wireless sensor networks and short-range wireless controllers caused the growing of ZigBee technology. ZigBee is a communication technology developed specifically for short-range, low rate, low-cost wireless transmission.There are some characteristic such as short-range, low rate, low cost, and low power. The ZigBee Aliance group developed the specifications of software, and IEEE 802.15.4 group developed the specifications of hardware. IEEE 802.15.4a impulse radio UWB physical layer is one of the ZigBee physical layers. In our study, we designed a baseband signal processing algorithm meeting the specifications of IEEE 802.15.4a. The data processing flow in transmitter followed the specifications. In receiver, we designed baseband algorithms based-on the non-coherent energy detection scheme. Our algorithm including packet detection, synchronization and demodulation, and considering the implementation of algorithm, reducing the complexity of hardware as possible and improving the efficiency. Finally, the system performance is 3.9dB better than the receiver sensitivity.

<p>The advanced signal processing systems of today require extreme data throughput and low power consumption. The only way to accomplish this is to use parallel processor architecture.</p><p>The aim of this thesis was to evaluate the use of parallel processor architecture in baseband signal processing. This has been done by implementing three demanding algorithms in LTE on Ambric Am2000 family Massively Parallel Processor Array (MPPA). The Ambric chip is evaluated in terms of computational performance, efficiency of the development tools, algorithm and I/O mapping.</p><p>Implementations of Matrix Multiplication, FFT and Block Interleaver were performed. The implementation of algorithms shows that high level of parallelism can be achieved in MPPA especially on complex algorithms like FFT and Matrix multiplication. Different mappings of the algorithms are compared to see which best fit the architecture.</p>

The advanced signal processing systems of today require extreme data throughput and low power consumption. The only way to accomplish this is to use parallel processor architecture. The aim of this thesis was to evaluate the use of parallel processor architecture in baseband signal processing. This has been done by implementing three demanding algorithms in LTE on Ambric Am2000 family Massively Parallel Processor Array (MPPA). The Ambric chip is evaluated in terms of computational performance, efficiency of the development tools, algorithm and I/O mapping. Implementations of Matrix Multiplication, FFT and Block Interleaver were performed. The implementation of algorithms shows that high level of parallelism can be achieved in MPPA especially on complex algorithms like FFT and Matrix multiplication. Different mappings of the algorithms are compared to see which best fit the architecture.