This thesis explores the use of an ASIP for handling O-RAN control data. A model application was constructed, optimized and profiled on a simple RV32-IMC core. The compiled code was analyzed, and the instructions “byte swap”, “pack”, bitwise extract/deposit” and “bit field place” were implemented. Synthesis of the core, and profiling of the model application, was done with and without each added instruction. Byte swap had the largest impact on performance (14% improvement per section, and 100% per section extension), followed by bitwise extract/deposit (10% improvement per section but no impact on section extensions). Pack and bit field place had no impact on performance. All instructions had negligible impact on core size, except for bitwise extract/deposit, which increased size by 16%. Further studies, with respect to both overall architecture and further evaluation of instructions to implement, would be necessary to design an ideal ASIP for the application.

This master thesis deals with the design of a RISC-V processor with bit manipulations instruction set extension. In this work, attention is paid to the description of the RISC-V instruction set and the CodAL language, which is used to describe the instruction sets and the processor architectures. The main goal of this work is to implement a model with a 32-bit address space, RISC-V basic instruction set and bit manipulations instruction set. The processor's design have two models, which one is instruction model and second is RTL model. The resulting parameters of the designed processor are measured using a Genus Synthesis Solution tool. The usability of bit manipulations based on decoder coverage is also included in the measurement.