This thesis presents a new cascaded iterative VLSI sorting architecture that can accelerate data sorting of variable-length sequences. The proposed sorter mainly consists of a central data memory block, a core comparison unit, and a special address generation module. Many fast sorting algorithms can be represented by a network of compare-and-swap (C&S) operations which can be divided into several processing steps. Instead of using parallel C&S functional units to perform C&S operations of the same sorting step, our comparison unit is composed of cascaded C&S units connected through data commutator such that different sorting steps can be processed simultaneously. The advantage of cascaded architecture is that the number of data memory accesses can be reduced by a factor equal to the number of cascaded stages. However, how to reduce the overhead of the data commutator becomes the most critical design issue. This thesis has explored the feature of C&S operation order in Bitonic sorting such that much simpler and more regular data commutator module can be achieved compared with the previous cascade design derived based on Batcher sorting. Therefore, the cascade level of our sorter architecture can be more than 2. A sample of 4-level cascade sorter has been implemented in our thesis. To generate the address sequence suitable for the proposed cascaded comparison unit, this paper proposes a low-cost address generator design based on the bit-permutation technique. Although high cascade level can lead to significant reduction of memory access which can help reducing the power dissipation, the issues of low hardware utilization for short data sequences and the increasing commutator overhead cannot be neglected. Therefore, to achieve further speed-up, this paper also adopts another parallelism approach for data sorter design by utilizing block-level C&S units which can compare a block of data at the same time. The block-level C&S units can be designed based on traditional Batcher¡¦s sorting network. Based on the proposed Bitonic cascade and Batcher¡¦s block sorting approaches, very fast and low-power sorter hardware can be achieved.

A partially parallel reconfigurable channel switch is constructed for use in DFBR. Its permutation can be changed while running without any interruption in the streams of data. Three approaches are tried: one based on asorting network, one based on memories and multiplexers and one based on a Clos network. Variants with the pattern stored in memories and in shift registers are tried. They are implemented in automatically generated Verilog and synthesized for an FPGA. Their cost in terms of area use, memory use and maximum clock frequency is compared and the results show that the Clos based approach is superior in all aspects and that pattern data should not be saved in shift registers. The work is open source and available for download at https://github.com/channelswitch/channelswitch. / En delvis parallel och delvis seriell kanalswitch för användning inom DFBR skapas. Dess permutation kan ändras medan den kör utan avbrott i dataströmmen. Tre alternativ undersöks: ett baserat ett sorteringsnätverk, ett baserat på minnen och multiplexrar och ett som baseras på Clos-nätverk. Versioner med mönsterdata sparad i skiftregister och i minnen prövas. De implementeras i automatiskt genererad Verilog och synthesiseras för en FPGA. Deras kostnad i areaanvändning, minnesanvändning och maximal klockfrekvens jämförs. Resultaten visar i princip att Clos-nätverken är bäst i alla avseenden och att mönsterdata ska sparas i RAM-minnen och inte i skiftregister. Arbetet är open source och kan laddas ner från https://github.com/channelswitch/channelswitch.