In hybrid pixel detector fabrication, high-density interconnection between focal plane array and the read-out integrated circuit is important. Bump bonding is the preferable assembly method, it is small in size, low cost, high performance and flexible I/O. Flip-chip bonding is a vertical connection technique of focal plane array and top substrate with solder bumps. In this paper, Flip-chip bonding by electroplated indium bumps is described. There are advantages of using indium as the solder material. It is relatively inexpensive, it has good thermal and electrical conductivity, it is ductile, and it is cryogenically stable. Indium bumps with a diameter of 30 µm are successfully prepared by an electroplating method, however removing indium conductive layer after electrodeposition is challenging. The corresponding electroplating indium bump process is also discussed. Electrical measurement was applied to detect the connection integrity of the flip-chip assemblies.

The 25 Ma Bumping Lake pluton ranges in composition from quartz diorite to granite with the granitic facies comprising approximately 90% of the pluton's surface area. The granite may be classified as calcalkaline, peraluminous and I-type with some Stype characteristics. A late-stage, mafic-poor facies fills cooling related extensional fractures. The pluton was passively emplaced into the Ohanapecosh Formation at a shallow level in the crust. Contact relationships vary from sharp where the contact is vertical to gradational at the roof of the pluton. Where gradational, stoped xenoliths from the roof of the pluton increase in size, angularity and retain more of their primary textures as the contact is approached. Spacial trends in major and trace elements support the interpretation that xenoliths were stoped and assimilated into the melt The predicted Rayleigh number for the pluton when molten is 107 and the predicted Reynolds number is approximately 10-9. Based on these values, the magma of the pluton probably did not convect, and if it did, convection was weak and not a significant process. Based on variations in Eu/Eu* and Sr values, plagioclase fractionation was an important process in the petrogenesis of the pluton. Additionally, fractionation of accessory minerals rich in light rare-earth elements (LREE) resulted in successive depletion of LREE with progressive differentiation. Two separate regions of the pluton are highly differentiated as indicated by high Si02 values, high Rb/Zr ratios, and low Zr and Ti02 values. Mapping by the author indicates that the pluton projects beneath the Mount Aix caldera. Dates of three tuffs derived from the caldera are equivalent to the pluton, and two of these tuffs are chemically indistinguishable from the granite facies of the pluton. This implies that the Bumping Lake pluton represents the chilled remains of the magma chamber that fed the Mount Aix caldera.

This paper presents the results of an ongoing effort to develop a direct solder bumping process for electronics packaging. The proposed process entails delivering molten droplets onto specific locations on electronic devices to form solder bumps. This study is focused on investigating droplet deposition behaviors that affect solder bump characteristics such as final bump volume, shape, and adhesion strength. The occurrence of droplet bouncing has a strong influence on these characteristics. The potential for a droplet to bounce in the absence of solidification was modeled in discrete stages based on energy conservation. Wetting and target surface roughness were identified as the critical parameters affecting bouncing. The experimental results showed that improvements in wetting and decreases in surface roughness retard bouncing. These observations agreed well with the trends predicted by the energy conservation based model. The knowledge acquired in this study is expected to contribute to the development of an efficient solder bumping process. / Singapore-MIT Alliance (SMA)

Microelectronics integration continuously follows the trend of miniaturisation for which the technologies enabling fine pitch interconnection are in high demand. The recent advancement in the assembly of Hybrid Pixel Detectors, a high resolution detecting and imaging device, is an example of where novel materials and processes can be applied for ultra-fine pitch interconnections. For this application, indium is often used for the fine pitch bump bonding process due to its unique properties that make it especially suitable, in particular in a cryogenic environment where some types of detector have to serve. Indium bumps are typically fabricated through vacuum evaporation at the wafer level; however, this thesis investigates an alternative low cost manufacturing process at the wafer scale for the deposition of indium micro-bumps through electroplating. The work has placed its emphasis on the requirements of future technologies which will enable a low temperature (<150oC), high density interconnection (> 40,000 IOs/cm2) with a high throughput and high production yield. This research is a systematic investigation of the wafer-scale indium bumping process through electrodeposition using indium sulphamate solution. An intensive experimental study of micro-bump formation has been carried out to elaborate the effects of two of the main electroplating factors that can significantly influence the quality of bumps in the course of electrodeposition, namely the current distribution and mass transport. To adjust the current density distribution, various waveforms of current input, including direct current (DC), unipolar pulse current and bipolar pulse reverse current, were employed in the experiments. To assist mass transportation prior to or during electroplating, acoustic agitation including ultrasonic agitation at 30 kHz frequency as well as megasonic agitation at 1 MHz, were utilised. The electrochemical properties of the indium sulphamate solution were first investigated using non-patterned plain substrates prior to indium bumping trials. This provided understanding of the microstructural characteristics of indium deposits produced by electroplating and, through cathodic polarisation measurements, the highest current density suitable for electrodeposition was achieved as approximately 30 mA/cm2 when electroplating was carried out at room temperature and with no agitation applied. The typical surface morphology of DC electroplated indium contained a granular structure with a surface feature size as large as 10 µm. Pulse and pulse reverse electroplating significantly altered the surface morphology of the deposits and the surface became much smoother. By introducing acoustic agitation, the current density range suitable for electrodeposition could be significantly expanded due to the greater mass transfer, which led to a higher speed of deposition with high current efficiency. Wafer-scale indium bumping (15 µm to 25 µm diameter) at a minimum pitch size of 25 µm was successfully developed through electroplating trials with 3 inch test wafers and subsequently applied onto the standard 4 inch wafers. The results demonstrate the capability of electroplating to generate high quality indium bumps with ultrafine pitch at a high consistency and yield. To maximise the yield, pre-wetting of the ultrafine pitch photoresist patterns by both ultrasonic or megasonic agitation is essential leading to a bumping yield up to 99.9% on the wafer scale. The bump profiles and their uniformity at both the wafer and pattern scale were measured and the effects of electrodeposition regimes on the bump formation evaluated. The bump uniformity and microstructure at the feature scale were also investigated by cross-sectioning the electroplated bumps from different locations on the wafers. The growth mechanism of indium bumps were proposed on the basis of experimental observation. It was found that the use of a conductive current thief ring can homogenise the directional bump uniformity when the electrical contact is made asymmetrically, and improve the overall uniformity when the electrical contact is made symmetrically around the periphery of the wafer. Both unipolar pulse electroplating and bipolar pulse reverse electroplating improved the uniformity of the bump height at the wafer scale and pattern scale, and the feature scale uniformity could be significantly improved by pulse reverse electroplating. The best uniformity of 13.6% for a 4 inch wafer was achieved by using pulse reverse electroplating. The effect of ultrasonic agitation on the process was examined, but found to cause damage to the photoresist patterns if used for extended periods and therefore not suitable for use throughout indium bumping. Megasonic agitation enabled high speed bumping without sacrifice of current efficiency and with little damage to the photoresist patterns. However, megasonic agitation tended to degrade some aspects of wafer scale uniformity and should therefore be properly coupled with other electroplating parameters to assist the electroplating process.

Conventional tin-lead solder alloys have been widely used in electronics interconnection owing to their properties such as low melting temperature, good ductility and excellent wettability on copper and other substrates. However, due to the worldwide legislation addressing the concern over the toxicity of lead, the usage of lead-containing solders has been phased out, thus stimulating substantial efforts on lead-free alternatives, amongst which eutectic Sn-Ag and Sn-Cu, and particularly Sn-Ag-Cu alloys, are promising candidates as recommended by international parties. To meet the increasing demands of advanced electronic products, high levels of integration of electronic devices are being developed and employed, which is leading to a reduction in package size, but with more and more input/output connections. Flip chip technology is therefore seen as a promising technique for chip interconnection compared with wire bonding, enabling higher density, better heat dissipation and a smaller footprint. This thesis is intended to investigate lead-free (eutectic Sn-Ag, Sn-Cu and Sn-Ag-Cu) wafer level solder bumping through electrodeposition for flip chip interconnection, as well as electroplating lead-free solderable finishes on electronic components. The existing knowledge gap in the electrochemical processes as well as the fundamental understanding of the resultant tin-based lead-free alloys electrodeposits are also addressed. For the electrodeposition of the Sn-Cu solder alloys, a methanesulphonate based electrolyte was established, from which near-eutectic Sn-Cu alloys were achieved over a relatively wide process window of current density. The effects of methanesulphonic acid, thiourea and OPPE (iso-octyl phenoxy polyethoxy ethanol) as additives were investigated respectively by cathodic potentiodynamic polarisation curves, which illustrated the resultant electrochemical changes to the electrolyte. Phase identification by X-ray diffraction showed the electrodeposits had a biphasic structure (β-Sn and Cu6Sn5). Microstructures of the Sn-Cu electrodeposits were comprehensively characterised, which revealed a compact and crystalline surface morphology under the effects of additives, with cross-sectional observations showing a uniform distribution of Cu6Sn5 particles predominantly along β-Sn grain boundaries. The electrodeposition of Sn-Ag solder alloys was explored in another pyrophosphate based system, which was further extended to the application for Sn-Ag-Cu solder alloys. Cathodic potentiodynamic polarisation demonstrated the deposition of noble metals, Ag or Ag-Cu, commenced before the deposition potential of tin was reached. The co-deposition of Sn-Ag or Sn-Ag-Cu alloy was achieved with the noble metals electrodepositing at their limiting current densities. The synergetic effects of polyethylene glycol (PEG) 600 and formaldehyde, dependent on reaching the cathodic potential required, helped to achieve a bright surface, which consisted of fine tin grains (~200 nm) and uniformly distributed Ag3Sn particles for Sn-Ag alloys and Ag3Sn and Cu6Sn5 for Sn-Ag-Cu alloys, as characterised by microstructural observations. Near-eutectic Sn-Ag and Sn-Ag-Cu alloys were realised as confirmed by compositional analysis and thermal measurements. Near-eutectic lead-free solder bumps of 25 μm in diameter and 50 μm in pitch, consisting of Sn-Ag, Sn-Cu or Sn-Ag-Cu solder alloys depending on the process and electrolyte employed, were demonstrated on wafers through the electrolytic systems developed. Lead-free solder bumps were further characterised by material analytical techniques to justify the feasibility of the processes developed for lead-free wafer level solder bumping.

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