1 |
Design and analysis of reconfigurable and adaptive cache structuresBond, Paul Joseph 08 1900 (has links)
No description available.
|
2 |
MatRISC : a RISC multiprocessor for matrix applications / Andrew James Beaumont-Smith.Beaumont-Smith, Andrew James January 2001 (has links)
"November, 2001" / Errata on back page. / Includes bibliographical references (p. 179-183) / xxii, 193 p. : ill. (some col.), plates (col.) ; 30 cm. / Title page, contents and abstract only. The complete thesis in print form is available from the University Library. / This thesis proposes a highly integrated SOC (system on a chip) matrix-based parallel processor which can be used as a co-processor when integrated into the on-chip cache memory of a microprocessor in a workstation environment. / Thesis (Ph.D.)--University of Adelaide, Dept. of Electrical and Electronic Engineering, 2002
|
Page generated in 0.1025 seconds