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Extended data cache prefetching using a reference prediction table /Kim, Donglok. January 1997 (has links)
Thesis (Ph. D.)--University of Washington, 1997. / Vita. Includes bibliographical references (leaves [76]-77).
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Cache characterization and performance studies using locality surfaces /Sorenson, Elizabeth S. January 2005 (has links) (PDF)
Thesis (Ph. D.)--Brigham Young University. Dept. of Computer Science, 2005. / Includes bibliographical references (p. 363-374).
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Scalable primary cache memory architecturesAgarwal, Vikas. John, Lizy Kurian, Keckler, Stephen W., January 2004 (has links) (PDF)
Thesis (Ph. D.)--University of Texas at Austin, 2004. / Supervisors: Lizy K. John and Stephen W. Keckler. Vita. Includes bibliographical references.
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A new N-way reconfigurable data cache architecture for embedded systemsBani, Ruchi Rastogi. Mohanty, Saraju, January 2009 (has links)
Thesis (M.S.)--University of North Texas, Dec., 2009. / Title from title page display. Includes bibliographical references.
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Directory-based Cache Coherence in SMTp Machines without Memory Overhead using Sparse DirectoriesKiriwas, Anton 01 January 2004 (has links)
As computing power has increased over the past few decades, science and engineering have found more and more uses for this new found computing power. With the advent of multiprocessor machines, we are achieving MIPS and FLOPS ratings previously unthought-of. Distributed shared-memory machines (DSM) are quickly becoming a powerful tool for computing, and the ability to build them from commodity off-the-shelf parts would be a great benefit to computing in general. In the paper entitled, "SMTp: An Architecture for Next-generation Scalable Multi-threading", Heinrich, et al. presents an architecture for a scalable DSM built from slightly modified machines capable of simultaneous multi-threading (SMT). In this architecture SMT -based machines are connected together via a high-speed network as DSMs with a directory-based cache coherence protocol. What is unique in SMTp is that the cache coherence protocol runs on the second thread in the SMT processors instead of running on an expensive, specialized memory controller. The results of this work show that SMTp can sometimes be even faster than dedicated hardware. In this thesis I intend to present the work on SMTp and extend its capabilities by removing the necessity for memory based directory backing by leveraging the work of Wolf-Dietrich Weber in sparse directories. The removal of the directory backing store will free a large percentage of main memory for work in the system while having only a minor impact on the cache miss rate of applications and overall system throughout.
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