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This works begins by providing motivation for additional research and political interest in the use of passenger railway systems as a method of ‘green’ transportation. Additional motivation for the adoption of energy saving methods within new and existing railway systems is also provided. This motivation stems from the relatively small carbon dioxide emissions per passenger kilometer and large quantity of electrical energy used in association with passenger railway systems. In specific cases, both theoretical analyses and experimental implementations of energy storage in railway systems have shown a reduction in electrical energy use and/or vehicle performance gains. Current railway energy storage systems (ESS) commonly make use of battery or electric double layer capacitor (EDLC) cells. A review of select energy storage technologies and their application in railway systems is provided. For example, the developing Qatar Education City People Mover system makes use of energy dense batteries and power dense EDLCs to provide the range and power needed to operate without a conventional railway power source between stations, formally called catenary free operation. As an alternative to combining two distinct energy storage technologies, this work looks at experimentally characterizing the performance of commercially available lithium ion capacitors (LiCs); a relatively new energy storage cell that combines characteristics of batteries and EDLCs into one cell. The custom cell testing apparatus and lab safety systems used by this work, and others, is discussed. A series of five tests were performed on two EDLC cells and five LiC cells to evaluate their characteristics under various electrical load conditions at multiple temperatures. The general conclusion is that, in comparison to the EDLC cells tested, the LiC cells tested offer a superior energy density however, their power capabilities are relatively limited, especially in cold environments, due to larger equivalent series resistance values. The second topic explored in this work is the development of a MATLAB based DC powered passenger vehicle railway simulation tool. The simulation tool is connected to the experimental analysis of EDLC and LiC cells by comparing the volume and mass of an energy storage system needed for catenary free (no conventional DC power supply) operation between train stations using either energy storage technology. A backward facing modelling approach is used to quantify the drive cycle electrical power demands as a function of multiple vehicle parameters and driving parameters (eg. acceleration rate, travel distance and time). Additional modelling methods are provided as a resource to further develop the simulation tool to include multiple vehicles and their interactions with the DC power supply. Completion of the multi-vehicle simulation tool with energy storage systems remains a task for future work. / Thesis / Master of Applied Science (MASc)

Voltage converters or charge pumps find their use in many circuits. They are extensively used in hand held devices as cell phones, pagers, PDA's and laptops. Some of the important issues relating to design of voltage regulators for handheld devices are size, efficiency and noise. Another important factor to be considered is the discharge characteristic of the various batteries used by the handheld devices. This thesis addresses the issues of tones present in the conventional switched capacitor voltage regulator. An alternate architecture with a delta-sigma control loop to eliminate this problem is proposed. Also discussed is a method to compute the efficiency of switched capacitor charge pumps. A test chip implementing the new architecture was fabricated in a 0.72-micron CMOS process. The results of the test chip verify the improved architecture. / Graduation date: 2002

It has been verified by theoretical analysis, circuit simulation and test that two switch transistors in parallel in a simple sample and hold circuit can be achieve high speed with low error voltage due to charge injection. The wide transistor provides low RC time constant when it is closed and the narrow one ensures a low error voltage. However, tradeoff can be made in a specific application. A concise analytical expression for switch-induced error voltage on a switched capacitor is derived in this thesis. It can help designer to make the optimum decision. Experimentally, it was found that the optimum size of the wide transistor is several times wider than the narrow one. Delayed clock scheme can be used to make charge injection signal-independent in a basic integrator structure. Using two transistors with different sizes and clock duty cycles in parallel can take advantage of the fast speed of the wide transistor and the small charge injection error of the small transistor. However, the combination of the two devices, including the size and clock duty cycles, should be chosen carefully to achieve the improvement. / Graduation date: 1998

In the first part of this thesis, RF specifications of the CSR Bluetooth module were tested rigorously by means of proper equipment setup and manipulation. The tested parameters in the transmitter include output power, spectrum and modulation characteristics. The tested parameters in the receiver include sensitivity and received signal strength indicator. The second part of this thesis was mainly focused on some mixed-signal integrated-circuit designs that can be generally applied to the Bluetooth RF front-end. The design examples include the phase frequency detector, charge pump, and frequency divider in the applications of phase-locked loop. A transconductance-capacitor low-pass filter with tunable cut-off frequencies was also designed to suppress the spurious signals from RF front-end into baseband.

Commericially available BaTiO3 powder was die-pressed to discs, and sintered by a two-stage firing consisting of reducing in low oxygen partial pressures (pO2) and re-oxidizing in a higher pO2 to simulate the industrial process of manufacturing the multi-layer ceramic capacitors(MLCC). Both undoped and MgO-doped discs as well as commercial MLCC chips, provided by Ferro Electronic Material Systems, have been investigated for sintered microstructures using the scanning electron microscopy (SEM) and transmission electron microscopy (TEM), crystalline phases using the X-ray diffractometry (XRD), and dielectric properties using the frequency response analysis. A comparison between the microstructures is made in order to look for the microstructure origin of the macroscopic behaviour, e.g. dielectric properties.It is found that the crystalline phases have changed frompredominantly tetragonal to pseudo-cubic with MgO > 0.5 mol.%. Apart from grain growth being effectively suppressed in MgO-doped compositions, grains containing the characteristic ferroelectric domains in undoped samples have decreased significantly in number. The indication is that Mg2+ dissolving into the BaTiO3 lattice, substituting for the Ti4+ site reduces the c/a ratio. However, unlike what was reported before, no direct experimental evidence is found to support that grain growth inhibition is effected by Mg2+ segregation to grain boundaries.Dislocation loops are observed ubiquitously in all samples, although bothMgO doping and low pO2 have decisive effect on their density in sintered grains. In MLCC chips, the microstructure is characterised by core-shell grains representing the dissolution of solutes, and modulated grains representing the ordering of chemical defects, e.g. substitutional defects and oxygen vacancies forming defect clusters.Residual pores located intragranularly in the MLCC chips are also observed, and its origin discussed. The formation of such pores is attributed to vacancy condensation which is enhanced by the increased oxygen vacancies due to MgO doping, as an acceptor, and by low pO2 firing.

Today’s thin-film passive components such as capacitors and inductors are limited to low volumetric density and large form-factors that pose as major roadblock to miniaturization of the power modules. These components are also placed far away from the IC’s leading to large interconnect parasitics and lower operating frequencies. Novel thin-film technologies with high densities and small form-factors are, therefore, required to enable miniaturization and performance at high frequencies. Glass- and silicon- based interposer technologies that utilize vertical through-via interconnections have shown way to improve power distribution network (PDN) performance with thin power-ground planes. However, integration of ultra-high density capacitors in such substrates has not yet been demonstrated. This thesis addresses these challenges with tantalum-based, silicon-integrated, ultrathin, high-density capacitors at higher operating frequencies with lower leakage properties (<0.01µA/µF). The anodization kinetics of tantalum pentoxide and the underlying leakage current mechanisms are investigated to provide optimal process guidelines. The thin-film Ta capacitors demonstrated capacitance density of 0.1 µF/mm2 at 1-10 MHz in form-factors of 50 µm, which corresponds to 6X higher volumetric density relative to commercial tantalum capacitors. An innovative approach to address incompatibility of tantalum electrodes with substrates is pursued by prefabricating the electrodes on a free-standing foil, which are then transferred onto the active wafer to form the capacitors on Si. The integration approach is designed to embed these thin tantalum capacitors on alternative substrates such as organic, glass or silicon, with copper via interconnections for lower parasitics. The thesis also explores titanium-based high-density capacitors with high-permittivity titania dielectric as a potential alternate high-density capacitor technology.

Tantalum capacitors are electronic components that are widely used in many types of devices. They are particularly valued for their exceptionally high capacitance and volumetric efficiency. One of the most vital performance parameters for this type of capacitor is the ability to handle unwanted AC ripple, since high levels of ripple can lead to overheating and capacitor failure. Yet the actual ripple limit for a capacitor has been historically difficult to quantify, and has been previously provided to customers only in the form of heavily padded estimates. Throughout the capacitor industry there has been significant demand for more realistic ripple ratings. The discussion here describes a new test system that has been designed to meet this demand for ripple characterization of wet tantalum capacitors.

In this thesis, novel design techniques have been proposed for implementing high-linearity SC circuits in a standard digital CMOS process. They use nonlinear MOSFET capacitors instead of linear double-poly capacitors. To reduce their nonlinearities, a bias voltage is applied to keep MOSFET capacitors in their accumulation regions. For further reduction of distortion, two capacitors can be connected in series or in parallel so that a first-order cancellation of the nonlinearity can be achieved. Experimental results demonstrated that the among these techniques series compensation is the most effective for reducing the nonlinearity of MOSFET capacitors. A novel predictive SC amplifier has been proposed for its insensitivity to op-amp imperfections. Experimental results show that the S/THD of the predictive SC amplifier was 10 dB larger than that of the non-predictive one. It was also shown that a predictive circuit was effective for reducing the nonlinearity caused by the op-amp and/or the MOSFET capacitors. It has been demonstrated that a two-stage op-amp with a large output swing can be fabricated in a standard digital CMOS process. The frequency compensation was accomplished using a source follower and a MOSFET capacitor. An SC amplifier using this two-stage op-amp and double-poly capacitors was fabricated, and it exhibited a large linear output range. A MOSFET-only digitally controlled gain/loss circuit was designed and fabricated in a 1.2�� CMOS process. It demonstrated that the series compensation is effective not only for a large output swing in an amplifier, but also for a large input swing in an attenuator. A pipeline D/A converter utilizing MOSFET capacitors was designed as another application of charge processing technique. It consisted of three parts: a V-Q conversion stage, a charge transfer stage, and a Q-V converter. A new switch configuration which enables the series compensation to have a large bias voltage has also been proposed. It was shown that it works well, and it will be helpful for low-voltage operation, too. / Graduation date: 1998

Oversampled delta-sigma modulation is one of the widely used A/D conversion techniques for narrow bandwidth signals. In this study several new lowpass and bandpass delta-sigma modulator architectures as well as novel pseudo-N-path integrators that can be used in implementing these architectures are proposed. By using multiplexing techniques the new lowpass delta-sigma modulator architectures exchange higher clock rates with hardware complexity. For a given oversampling ratio (OSR), the multiplexed first-order delta-sigma modulator achieves a higher resolution. Guaranteed stability is a very desirable feature of these structures. The multi-loop delta-sigma modulator architecture similarly reduces the number of integrators needed to achieve high-resolution conversion for a given OSR. To ensure stability a quantizer with (N+1) bits must be used, where N is the number of loops, or in other words, the order of the delta-sigma modulator. Digital correction or randomizing techniques can be used to eliminate the performance reduction due to digital-to-analog- (D/A) converter nonlinearity error [59], [64]. Bandpass delta-sigma modulators are useful for applications such as AM radio receivers, spectrum analyzers, and digital wireless systems. Using z --> -z[superscript N] or z --> z[superscript N] mapping, a low pass delta-sigma modulator can be transformed to a bandpass one. One of the methods to implement the loop filters in bandpass delta-sigma modulators is to use Pseudo-N-Path (PNP) switched-capacitor (SC) integrators. The advantage is that the center frequency occurs exactly at an integer division of the sampling frequency because of the number of physical paths. To achieve maximum resolution, integrators that do not suffer from clock feedthrough peaks are needed. The proposed differential and single-ended novel PNP integrators address this problem [76]. To keep the opamp specifications less stringent while achieving high resolution, these PNP integrators have been further improved with gain compensation techniques [53]. / Graduation date: 1997