The thesis is composed of two topics : a charger circuit of Li-ion batteries for wireless biomedical systems and a capacitor-less low dropout regulator¡]LDO¡^. The first topic discloses a charger circuit of Li-ion batteries using 2P4M 0.35-£gm CMOS process, which comprises a small bias circuit, a comparator with hysteresis, a transistor voltage divider circuit, a power MOS, and a Li-ion charger with a cut-off voltage and a recharge voltage. The proposed design receives a 13.56 MHz carrier with 5¡Ó0.2 V amplitude to charge the Li-ion batteries with a small constant current. The second topic reveals a low dropout regulator ¡]LDO¡^ without capacitor load and ESR, including a bias circuit, an error amplifier, and a Flipped Voltage Follower circuit generating a stable output voltage independent on different loads. The proposed design improves the input voltage limitation of Flipped Voltage Follower by compensating phase margin such that the proposed design shows a good transient response and stability without any output capacitor. The proposed LDO is implemented by 1P6M 0.18-um CMOS process, which can operate correctly given an input voltage range from 3.3~4.2 V.

Low Dropout Regulators (LDOs) are extensively used in portable applications like mobile phones, PDAs and notebooks. These portable applications demand high power efficiency and low output voltage ripple. In addition to these, the radio circuits in these applications demand high power supply rejection (PSR). The output voltage of a conventional DC/DC converter (generally switched mode) has considerable ripple which feeds as input to these LDOs. And the challenge is to suppress these ripples for wide range of frequencies (for radio units) to provide clean supply. Enhanced buffer based compensation is proposed for the fully on-chip CMOS LDO which stabilizes the loop for different load conditions as well as improve the power supply rejection (PSR) until frequencies closer to open loop‟s unity-gain frequency. The stability and PSR are totally valid even for load capacitor varying from 0 to 100 pF. The proposed capacitor-less LDO is fabricated in On-Semi 0.5 μm fully CMOS process. Experimental results confirm a PSR of -30 dB till 420 KHz for the maximum load current of 50mA. The load transients of the chip shows transient glitches less than 90 mV independent of output capacitance.