Clock multipliers are among the most critical elements in high speed digital circuits. Power consumption, area, jitter and wide tuning range are key design metrics in these circuits. To provide a wide range of clock frequencies, Digitally Controlled Ring Oscillators (DCROs), whose frequencies are discretely tuned using a Frequency Code Word (FCW), have been investigated in recent studies. They have several advantages over LC-based Voltage Controlled Oscillators (VCO) including simplicity of design, small die area (i.e. no large inductors), better compatibility with deep submicron CMOS processes,ability to offer multiple output phases, and wider tuning range.A compact differential Injection Locked Clock Multiplier (ILCM) based on an injection locked DCRO is implemented in this thesis. As the transistor features continuously shrink and the supply voltage is reduced, ILCMs are becoming more prone to issues such as increased effect of random mismatch, increased device noise, susceptibility of the design to noise coupling and vulnerability to Process Voltage and Temperature (PVT) variations. Furthermore, ILCMs in recent System on a Chip (SoCs) have stringent design requirements including accurate frequency tuning, fine fractional resolution, high levels of integration and better amenability to technology scaling. In the proposed ILCM, multiple techniques were used to address deep submicron CMOS design challenges, as well as modern applications’ requirements. The design is fully digital, synthesizable and automatically placed and routed. All circuit blocks were implemented using digital design flow and designed using a Hardware Description Language (HDL). This allows the design to be more easily ported to deep submicron processes. Online or offline PVT calibration can be performed using a replica oscillator and high speed digital counters to track frequency drifts with PVT variations. A DCRO based on a matrix structure has been utilized to reduce period variations due to random mismatch. The DCRO is built up from pseudo differential delay cells to enhance design immunity to noise coupling. The key thesis contributions are implementing a new DCRO structure using fully syntheziable differential structure, utilizing a novel PVT calibrator that can compensate for frequency mismatch between the main DCRO and its replica, and using a low complexity fractional ILCM technique that achieves a fine fractional resolution with few number of ring oscillator stages.Designed in a TSMC 65 nm GP CMOS process with no analog or RF enhancements, the proposed ILCM frequency ranges from 1.0 to 1.8 GHz and occupies 124:5 m 170 m of chip area. The ILCM can operate in integer or fractional mode for multiplication ratios up to 9. At 1.7 GHz and 1.1 V, the measured integrated RMS jitter (1 kHz to 30 MHz) for the 3rd and 9th multiplication factors are 197 fs and 381 fs, respectively. The ILCM consumes 13.25 mW of power and has a fraction resolution of fref=32. Furthermore, it achieves a jitter-power FOM of −241 dB, when measured at room temperature and 1.1 V. When tested in the presence of switching noise, it provides up to 7 dB improvement in phase noise when compared to a single ended version of the ILCM. In the presence of voltage variations (from 0.9 V to 1.1 V) and temperature variations (from 30 C to 70 C), the maximum integrated RMS jitter variation observed was 50 fs.