Phase locked loops (PLL) are used in a variety of RF integrated applications because of their ability to generate precise clock signals. These applications include clock recovery systems, frequency synthesizers and frequency multipliers. In order to achieve small size and low cost targets, the PLLs must be fully integrated on-chip with all the necessary components. Unfortunately, the filtering requirement for the low pass filter (LPF) demands a large silicon area, or the use of external capacitors. Moreover, high-density recording and high data rates for image transfer systems in wireless communication require more fully integrated LSI. The main goal of this study is to find area efficiency with fully on-chip design, and to provide a solution to improve the phase noise level without occupying a large area or using off-chip components. Moreover, to reduce the phase noise level, it is necessary to desensitize the VCO control when the loop is in the "lock zone". The introduced phase noise enhancement (PNE) will smartly reduce the phase noise without degrading the settling time by reducing the loop gain in the lock conditions.

A phase-locked loop commonly known as PLL is widely used in communication systems. A PLL is used in radio, telecommunications, modulation and demodulation. It can be used for clock generation, clock recovery from data signals, clock distribution and as a frequency synthesizer. Most electronic circuits encounter the problem of the clock skew. The clock Skew for a synchronous circuit is defined as the difference in the time of arrival between two sequentially adjacent registers. The registers and the flip-flops do not receive the clock at the same time. The clock signal in a normal circuit is generated with an oscillator, oscillator produces error, due to which there is a distortion from the expected time interval. The PLLs are used to address the problem. A phase-locked loop works to ensure the time interval seen at the clocks of various registers and the flip-flops match the time intervals generated by the oscillator. PLLs are trivial and an essential part of the micro-processors. Traditional PLLs are designed to work as an analog building block, but it is difficult to integrate them on a digital chip. Analog PLLs are less affected by noise and process variations. Digital PLLs allow faster lock time and are used for clock generation in high performance microprocessors. A digital PLL has more advantages as compared to an analog PLL. Digital PLLs are more flexible in terms of calibration, programability, stability and they are more immune to noise. The cost of a digital PLL is less as compared to its analog counter part. Digital PLLs are analogous to the analog PLLs, but the components used for implementing a digital PLL are digital. A digitally controlled oscillator (DCO) is utilized instead of a voltage controlled oscillator. A time to digital converter(TDC) is used instead of the phase frequency detector. The analog filter is replaced with a digital low pass filter. Phase-locked loop is a very good research topic in electronics. It covers many topics in the electrical systems such as communication theory, control systems and noise characterization. This project work describes the design and simulation of miscellaneous blocks of an all-digital PLL for the 60 GHz band. The reference frequency is 54 MHz and the DCO output frequency is 2 GHz to 3 GHz in a state-of the-art 65 nm process, with 1 V supply voltage. An all-digital PLL is composed of digital components such as a low pass filter, a sigma delta modulator and a fractional N /N +1 divider for low voltage and high speed operation. The all-digital PLL is implemented in MATLAB and then the filter, a sigma delta modulator and a fractional N /N +1 divider are implemented in MATLAB and Verilog-A code. The sub blocks i.e full adder, D flip-flop, a digital to digital converter, a main counter, a prescalar and a swallow counter are implemented in the transistor level using CMOS 65nm technology and functionality of each block is verified.

This report tested the possibility of using induction as a mean for transferring data and power so that it can be implemented as a communication medium between a terminal and measuring head mounted in a measuring frame. This would eliminate the need for the cable bunches that are used today. For testing, signal generators were used to generate FSK-signals and were transferred with the help of inductors to the oscilloscope for signal detection, this to see how the coils used in the tests behaved. Simulations of a PLL were performed to see how good it could handle FSK-demodulation. With the help of a PLL IC and the simulations a working FSK-demodulator could be assembled. This showed that the simulations and reality is in good agreement. The final results shows that it’s possible to transfer FSK-modulated data in either direction but that the desired effect isn’t possible to transfer because of the existing coupling factor that exist in the coils core used in the test. / I denna rapport testas möjligheterna att använda elektromagnetisk induktion för att överföra data och elektrisk effekt för kommunikation media mellan terminal och mäthuvudet i en mätram som används vid framställning av papper. Detta skulle kunna eliminera behovet av de besvärliga kabelbuntar som används idag. I testerna används signalgeneratorer för att generera en FSK-modulerad signal som representerar den data som överförs via spolar. Efter detektering studeras signalen på ett oscilloskop för att se hur de spolar som användes i testerna beter sig. Även simuleringar av en PLL utfördes för att se hur bra den kunde hantera FSK-demodulering. Med hjälp av kunskaper från simuleringar och en PLL IC-krets kunde en fungerande FSK-demodulator byggas ihop. Det visade att simuleringarna och verkligheten stämmer bra överens. De slutgiltiga resultaten visar att det är möjligt att skicka FSK-modulerad data i båda riktningar utan komplikationer. Den önskade effektöverföringen visar sig dock inte vara möjlig på grund av den mycket låga kopplingsfaktorn mellan spolarna som användes i testet.

Demand for low cost Serializer and De-serializer (SerDes) integrated circuits has increased due to the widespread use of Synchronous Optical Network (SONET)/Gigabit Ethernet network and chip-to-chip interfaces such as PCI-Express (PCIe), Serial ATA(SATA) and Fibre channel standard applications. Among all these applications, clock data recovery (CDR) is one of the key design components. With the increasing demand for higher bandwidth and high integration, Complementary metal-oxidesemiconductor (CMOS) implementation is now a design trend for the predominant products. In this research work, a fully integrated 10Gb/s (OC-192) CDR architecture in standard 0.18 μ m CMOS is developed. The proposed architecture integrates the typically large off-chip filter capacitor by using two feed-forward paths configuration to generate the required zero and poles and satisfies SONET jitter requirements with a total power dissipation (including the buffers) of 290mW. The chip exceeds SONET OC-192 jitter tolerance mask, and high frequency jitter tolerance is over 0.31 UIpp by applying PRBS data with a pattern length of 231-1.The implementation is the first fully integrated 10Gb/s CDR IC which meets/exceeds the SONET standard in the literature. The second proposed CDR architecture includes an adaptive bang-bang control algorithm. For 6MHz sinusoidal jitter modulation, the new architecture reduces the tracking error to 11.4ps peak-to-peak, versus that of 19.7ps of the conventional bangbang CDR. The main contribution of the proposed architecture is that it optimizes the loop dynamics by adjusting the bang-bang bandwidth adaptively to minimize the steady state jitter of the CDR, which leads to an improved jitter tolerance performance. According to simulation, the jitter performance is improved by more than 0.04UI,which alleviates the stringent 0.1UI peak to peak jitter requirements in the PCIe/Fibre channel/Sonet Standard.

This thesis introduces a multipass loop voltage controlled ring oscillator. The proposed structure uses cross-coupled PMOS transistors and replica bias with coarse/fine control signal. The design implemented in TSMC 90 nm CMOS technology, 0.9V power supply with frequency tuning range 481MHz to 4.08GHz and -94.17dBc/Hz at 1MHz offset from 4.08GHz with 26.15mW power consumption.

A PLL-based frequency shift measurement system for chemical and biological sensing was developed and implemented in the form of two discrete electronic assemblies. One of the assemblies consists of a VCO which contains a microwave resonator sensor while the other assembly contains commercially available PLL and MCU devices, as well as various other discrete components. When mated together, a PLL-based frequency synthesizer is realized, the output frequency of which is ~4.5 GHz. The system is used to measure the frequency shift exhibited by the frequency synthesizer when several commonly-known chemical substances are applied to the microwave resonator sensor test fixture. Because the amount of measured frequency shift is proportional to the dielectric constant of a given material under test (MUT), this system can potentially be used as part of a chemical identification system. This measurement system is also attractive in that it represents a stand-alone or 'self-contained' system which does not require usage of any additional expensive and bulky electronic diagnostic equipment such as a network analyzer or signal generator, making it a relatively inexpensive and portable solution. Attempts to use the system to measure frequency shift resulting from application of various common chemical substances to the sensor fixture results in derivation of dielectric constant values which hold very close agreement (+/-2%) to the published/theoretical dielectric constant values for each respective chemical substance.

An all-digital phase locked loop for WiGig systems was implemented. The developedall-digital phase locked loop has a targeted frequency range of 2.1-GHz to2.5-GHz. The all-digital phase locked loop replaces the traditional charge pumpbased analog phase locked loop. The digital nature of the all-digital phase lockedloop system makes it superior to the analog counterpart.There are four main partswhich constitutes the all-digital phase locked loop. The time-to-digital converteris one of the important block in all-digital phase locked loop. Several time-to-digital converter architectures were studied and simulated. TheVernier delay based architecture and inverter delay based architecture was designedand evaluated. There architectures provided certain short comings whilethe pseudo-differential time-to-digital converter architecture was chosen, becauseof it’s less occupation of area. Since there exists a relationship between the sizeof the delay cells and it’s time resolution, the pseudo-differential time-to-digitalconverter severed it’s purpose. The whole time-to-digital converter system was tested on a 1 V power supply,reference frequency 54-MHz which is also the reference clock Fref , and a feedbackfrequency Fckv 2.1-GHz. The power consumption was found to be around 2.78mW without dynamic clock gating. When the clock gating or bypassing is done,the power consumption is expected to be reduced considerably. The measuredtime-to-digital converter resolution is around 7 ps to 9 ps with a load variation of15 fF. The inherent delay was also found to be 5 ps. The total output noise powerwas found to be -128 dBm.

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In the early 1980s and 1990s, the first- and second-generation networks in wireless communication, called 1G and 2G, were introduced with only limited data connectivity in the world. The former could only transfer voices while the latter could transfer voices and messages. By the early 2000s, however, the 3G networks began working and let people have real access to the internet. The greater functionality enabled by 4G networks evolved from increased demand for higher data rates in the early 2010s. Nowadays, we are totally engaged in 4G world of LTE (Long Term Evolution) owing to the eruptive increase of mobile internet in smart phones or other mobile devices. The 5G networks are categorized into two branches according to their frequencies: (i) sub-6 GHz (700 MHz to 6 GHz) and (ii) near-millimeter wave (25 to 30 GHz). Commonly used applications are included in the sub-6 GHz, also called the Internet-of-Everything (IoE) and Internet-of-Things (IoT). To fulfill the date rate required for 5G applications, implementing complex systems is necessary. Consequently, new challenges are imposed to implement these systems such as noise performance and output power. At the heart of these systems lie frequency synthesizers. Frequency synthesizers are used to up or down convert the carrier signal in communication systems. Phase-locked loops (PLLs) are routinely utilized for frequency synthesis in Radio Frequency (RF)/mm-wave transceivers. The main challenges to design a PLL are phase noise (PN) or jitter, as well as power consumption. The main objective of this thesis is to carry out research on a fully integrated analog PLL fractional-N frequency synthesizer for 5G wireless communication and IoE/IoT applications in sub-6 GHz. To do this, we have studied the trends in the research of LC-VCOs (voltage-controlled oscillators) and identified the methods for going towards a low flicker-noise corner. Then, we have implemented the designed LC-VCO which is the main noise source in PLLs. In the final step we have designed the sub-blocks of the fractional-N analog frequency synthesis. The sub-blocks have been optimized to have less power dissipations. The implementation of a fully integrated analog PLL fractional-N frequency synthesizer is done in 180-nm standard CMOS technology (TSMC). It covers two frequency ranges including 2.4 to 2.48 GHz and 5 to 5.825 GHz. The phase noise at 10KHz varies between -94 dBc/Hz to -115dBc/Hz. / Thesis / Doctor of Philosophy (PhD) / The data rate in wireless, cellular communications, and wireline keeps growing by nearly 10 times per 5 years. To fulfill such date rate, implementing complex systems is necessary. Consequently, new challenges are imposed to implement these systems such as noise performance and output power. At the heart of these systems lie frequency synthesizers. Frequency synthesizers are used to up or down convert the carrier signal in communication systems. Phase-locked loops (PLLs) are routinely utilized for frequency synthesis in Radio Frequency (RF)/mm-wave transceivers. The main challenges to design a PLL are phase noise (PN) or jitter, as well as power consumption. This dissertation aims to implement an ultra-low power and low jitter frequency synthesizer for 5G wireless communication and IoE/IoT applications in 180-nm standard CMOS technology (TSMC). An analog PLL is used in this frequency synthesizer.

Fully integrated Ultra-Wideband (UWB) RFIC transmitters are designed in Si-based technologies for applications such as wireless communications or sensor networks. UWB technology offers many unique features such as broad bandwidth, low power, accurate position location capabilities, etc. This research focuses on the RFIC front-end hardware design issues for proposed UWB transmitters. Two different methods of multiband frequency generation ----- using switched capacitor VCO tanks and frequency mixing with single sideband mixers ----- are explored in great detail. To generate the required UWB signals, pulse generators are designed and integrated into the transmitter chips. The first prototype UWB transmitter is designed in Freescale Semiconductor 0.18μm SiGe BiCMOS technology for operation over three 500 MHz bands at center frequencies of 4.6/6.4/8.0 GHz, and generates pulses supporting differential BPSK modulation. The transmitter output frequency is controlled by a two-bit code which sets the state of a switched capacitor tank array for coarse tuning of the VCO. While selecting between the different bands, the transmitter is capable of settling and re-transmitting in less than 0.7μs using an integrated, wide band phase-locked loop (PLL). Various issues such as mismatch/inaccuracy of the pulses and high power consumption of the prescaler were identified during the first design and were addressed in subsequent design revisions. The pulse generator is a critical part of the proposed UWB transmitter. The initial pulse generator design used CMOS delay lines and logic gates to synthesize the required pulse bandwidth; however this approach suffered from inaccurate pulse timing control due to delay time sensitivity to device modelling and process variations. Subsequently, a novel pulse generator design capable of achieving accurate timing control was implemented using digital logic and a fixed oscillator frequency to provide timing information, integrated into a modified transmitter circuit, and subsequently fabricated in Jazz Semiconductor's 0.18μm CA18 RFCMOS process. Experimental results confirm the generation of accurate one-nanosecond pulses. Finally, a new multiband UWB transmitter based on a new single sideband (SSB) resistive mixer with superior linearity and zero static power consumption was also designed and fabricated using Jazz CA13 0.13μm RF CMOS process. This design is based on a fixed frequency phase-locked VCO and generates different bands through frequency mixing. In the prototype design, two additional carrier frequencies are generated from the VCO center frequency (5 GHz) by mixing it with its output divided-by-4 (1.25 GHz). By switching the relative I/Q phases of the LO/IF inputs to this single side band mixer, either the upper side band (6.25 GHz) or lower side band (3.75 GHz) frequency is selected at the mixer output, while the other sideband is rejected. Simulation results show that the transmitter is capable of generating the desired carrier frequencies while suppressing the image component by more than 40 dB. Overall, this work has explored various aspects of UWB transmitter design and implementations in fully integrated silicon chips. The major contributions of this work include: proposed hardware architectures for pulse-based multiband UWB transmitters; implemented a fully integrated multiband UWB transmitter with embedded phase-locked switched-tank VCO capable of wide frequency tuning; demonstrated an all digital pulse generator capable of generating accurate one-nanosecond pulse trains in the presence of various mismatches; and investigated resistive SSB mixer topologies and their implementation in a multiband UWB generation architecture. / Ph. D.