Demand for low cost Serializer and De-serializer (SerDes) integrated circuits has increased due to the widespread use of Synchronous Optical Network (SONET)/Gigabit Ethernet network and chip-to-chip interfaces such as PCI-Express (PCIe), Serial ATA(SATA) and Fibre channel standard applications. Among all these applications, clock data recovery (CDR) is one of the key design components. With the increasing demand for higher bandwidth and high integration, Complementary metal-oxidesemiconductor (CMOS) implementation is now a design trend for the predominant products. In this research work, a fully integrated 10Gb/s (OC-192) CDR architecture in standard 0.18 μ m CMOS is developed. The proposed architecture integrates the typically large off-chip filter capacitor by using two feed-forward paths configuration to generate the required zero and poles and satisfies SONET jitter requirements with a total power dissipation (including the buffers) of 290mW. The chip exceeds SONET OC-192 jitter tolerance mask, and high frequency jitter tolerance is over 0.31 UIpp by applying PRBS data with a pattern length of 231-1.The implementation is the first fully integrated 10Gb/s CDR IC which meets/exceeds the SONET standard in the literature. The second proposed CDR architecture includes an adaptive bang-bang control algorithm. For 6MHz sinusoidal jitter modulation, the new architecture reduces the tracking error to 11.4ps peak-to-peak, versus that of 19.7ps of the conventional bangbang CDR. The main contribution of the proposed architecture is that it optimizes the loop dynamics by adjusting the bang-bang bandwidth adaptively to minimize the steady state jitter of the CDR, which leads to an improved jitter tolerance performance. According to simulation, the jitter performance is improved by more than 0.04UI,which alleviates the stringent 0.1UI peak to peak jitter requirements in the PCIe/Fibre channel/Sonet Standard.

Baud-rate clock recovery (CR) is gradually gaining popularity in modern serial data transmission systems since these CR techniques do not require edge-samples for extracting timing information. However, previous baud-rate techniques for high-speed serial links either rely on specific 4-bit patterns or uncorrelated random data. This work describes the modeling and design of analog filter front-end aided baud-rate CR schemes. Unlike other baud-rate schemes, this technique is not constrained by the properties of the input random data. Firstly, the thesis develops a hardware-efficient baud-rate algorithm that requires only the slope information of the incoming random data. Called modified sign-sign minimum mean squared error (SSMMSE), this algorithm adjusts the clock sampling phase until the slope is zero through a bang-bang control loop. Secondly, the performance of a modified SSMMSE phase detector is investigated and compared with a conventional edge-sampled phase detector. It is shown that, at severe noise levels, the proposed modified SSMMSE method has better performance compared to the edge-sampled method for equal loop bandwidths.Thirdly, the thesis investigates different hardware-efficient slope detection techniques. Both passive and active filter based slope detection techniques are demonstrated in this work. In addition to slope generation, the active filter performs linear equalization as well. However, the passive filter generates the slope information at higher speeds than the active filter and also consumes less power. The two filters are used to recover a 2-GHz clock by using an external bang-bang loop. In short, the thesis demonstrates that area and power savings can be achieved by utilizing slope information from front-end filters without compromising the performance of the CR unit.

Baud-rate clock recovery (CR) is gradually gaining popularity in modern serial data transmission systems since these CR techniques do not require edge-samples for extracting timing information. However, previous baud-rate techniques for high-speed serial links either rely on specific 4-bit patterns or uncorrelated random data. This work describes the modeling and design of analog filter front-end aided baud-rate CR schemes. Unlike other baud-rate schemes, this technique is not constrained by the properties of the input random data. Firstly, the thesis develops a hardware-efficient baud-rate algorithm that requires only the slope information of the incoming random data. Called modified sign-sign minimum mean squared error (SSMMSE), this algorithm adjusts the clock sampling phase until the slope is zero through a bang-bang control loop. Secondly, the performance of a modified SSMMSE phase detector is investigated and compared with a conventional edge-sampled phase detector. It is shown that, at severe noise levels, the proposed modified SSMMSE method has better performance compared to the edge-sampled method for equal loop bandwidths.Thirdly, the thesis investigates different hardware-efficient slope detection techniques. Both passive and active filter based slope detection techniques are demonstrated in this work. In addition to slope generation, the active filter performs linear equalization as well. However, the passive filter generates the slope information at higher speeds than the active filter and also consumes less power. The two filters are used to recover a 2-GHz clock by using an external bang-bang loop. In short, the thesis demonstrates that area and power savings can be achieved by utilizing slope information from front-end filters without compromising the performance of the CR unit.

The topic of this thesis is to propose a dual-tracking clock data recovery device and method for LVDS. Particularly, it is related to a high speed data transmission which utilizes phase-locked loops (PLL) to trace and track two eyes (left eye and right eye), called dual-tracking, to align data sampling at the middle of data eye. Hence, the detection of the data is ensured to be optimal and the BER (bit error rate) is drastically reduced.

International Telemetering Conference Proceedings / October 20-23, 2003 / Riviera Hotel and Convention Center, Las Vegas, Nevada / In many test ranges, it is often required to acquire a number of telemetry streams and to process the data simultaneously. Frequently, the streams have different delay characteristics, requiring temporal alignment before the processing step. It is desired to have the capability to align these streams so that the events in each stream are coincident in time. Terawave Communications has developed technology to perform temporal alignment for a number of streams automatically. Additionally, the algorithm performs the delay compensation independent of the source data rate of each stream. Terawave will present the algorithm and share the results of their testing in a test installation.

International Telemetering Conference Proceedings / October 26-29, 1998 / Town & Country Resort Hotel and Convention Center, San Diego, California / The telemetry and aerospace communities require communications equipment providing various modulation and demodulation formats. One format, with application in Space Ground Link Subsystems (SGLS), utilizes a Ternary (tri-tone) Frequency Shift-Keyed (FSK) signal Amplitude Modulated (AM) by a triangle waveform. Historically, SGLS equipment has operated with a fixed tri-tone frequency set (e.g., 65 kHz, 76 kHz and 95 kHz). The need for additional transmission channels and increased bandwidth efficiency creates the requirement for equipment with the flexibility to generate and receive varied and higher frequency tone sets. Combining analog and digital techniques, GDP Space Systems has developed the FDT001. It is an FSK/AM detector which recovers a bit rate clock at one of four selectable bit rates and reproduces ternary FSK modulation data over a widely tunable range of tone frequencies. The tuning range is expanded by using two methods of digital frequency discrimination. The following paper describes the design of the FDT001.

<p>POTS (Plain Old Telephony Service) systems have traditionally been connected via synchronous connections. When installing new nodes in the telephone network, they may sometimes be connected via packet networks such as Ethernet. Ethernet is an asynchronous network which means that nodes connected to the network don’t have access to the same clock frequency if it is not provided in some other way. If two nodes have different clock frequency, the receiver’s buffer will eventually overflow or starve. While not being a severe problem for telephony, devices used for data transmission, e.g. modems and fax will not be able to function properly. To avoid this it is necessary to synchronize the nodes.</p><p>This thesis investigates methods to synchronize nodes connected over Ethernet by simulating them in Matlab. The simulations show that under certain circumstances it is possible to produce a clock signal conforming to relevant standards.</p>

POTS (Plain Old Telephony Service) systems have traditionally been connected via synchronous connections. When installing new nodes in the telephone network, they may sometimes be connected via packet networks such as Ethernet. Ethernet is an asynchronous network which means that nodes connected to the network don’t have access to the same clock frequency if it is not provided in some other way. If two nodes have different clock frequency, the receiver’s buffer will eventually overflow or starve. While not being a severe problem for telephony, devices used for data transmission, e.g. modems and fax will not be able to function properly. To avoid this it is necessary to synchronize the nodes. This thesis investigates methods to synchronize nodes connected over Ethernet by simulating them in Matlab. The simulations show that under certain circumstances it is possible to produce a clock signal conforming to relevant standards.

In this dissertation I investigated a multi-channel and multi-bit rate all-optical clock recovery device. This device, a birefringent Fabry-Perot resonator, had previously been demonstrated to simultaneously recover the clock signal from 10 wavelength channels operating at 10 Gb/s and one channel at 40 Gb/s. Similar to clock signals recovered from a conventional Fabry-Perot resonator, the clock signal from the birefringent resonator suffers from a bit pattern effect. I investigated this bit pattern effect for birefringent resonators numerically and experimentally and found that the bit pattern effect is less prominent than for clock signals from a conventional Fabry-Perot resonator.I also demonstrated photonic balancing which is an all-optical alternative to electrical balanced detection for phase shift keyed signals. An RZ-DPSK data signal was demodulated using a delay interferometer. The two logically opposite outputs from the delay interferometer then counter-propagated in a saturated SOA. This process created a differential signal which used all the signal power present in two consecutive symbols. I showed that this scheme could provide an optical alternative to electrical balanced detection by reducing the required OSNR by 3 dB.I also show how this method can provide amplitude regeneration to a signal after modulation format conversion. In this case an RZ-DPSK signal was converted to an amplitude modulation signal by the delay interferometer. The resulting amplitude modulated signal is degraded by both the amplitude noise and the phase noise of the original signal. The two logically opposite outputs from the delay interferometer again counter-propagated in a saturated SOA. Through limiting amplification and noise modulation this scheme provided amplitude regeneration and improved the Q-factor of the demodulated signal by 3.5 dB.Finally I investigated how SPM provided by the SOA can provide a method to reduce the in-band noise of a communication signal. The marks, which represented data, experienced a spectral shift due to SPM while the spaces, which consisted of noise, did not. A bandpass filter placed after the SOA then selected the signal and filtered out what was originally in-band noise. The receiver sensitivity was improved by 3 dB.

Single-frequency and mode-locked silver film ion-exchanged glass waveguide lasers as well as all-optical clock recovery based on birefringent fiber resonators have been experimentally and theoretically studied. The theory, modeling and fabrication process of silver film ion-exchange techniques, have been discussed and presented.The UV-written gratings on both IOG-1 active and passive glass have been studied. For the first time, with a high quality narrowband grating UV-printed on the passive section of a hybrid glass, a DBR waveguide single-frequency laser is demonstrated with the linewidth less than 1 MHz and the output power of 9 mW.Novel saturable absorbers based on a fiber taper embedded in carbon nanotubes (CNTs)/polymer composite were demonstrated. The saturable absorbers were utilized to build mode-locked fiber lasers, which were studied experimentally. A mode-locked ring laser utilizing an Er-Yb-codoped glass waveguide as the gain medium was also demonstrated. In addition, short cavity mode-locked waveguide lasers with CNTs film on the top were theoretically investigated, which shows a short cavity mode-locked waveguide laser is very promising.A new concept to perform multi-channel multi-rate all-optical clock recovery based on birefringent fiber-optic waveguide resonators was discussed. The concept has been advanced to polarization-insensitive operation. The experimental results, obtained as a proof-of-concept, agree well with numerical simulations.