The main scope of this thesis is to implement a new architecture of a high bandwidth phase-locked loop (PLL) with a large operating frequency range from 100~MHz to 1~GHz in a 150~$nm$ CMOS process. As PLL is the time-discrete system, the new architecture is mathematically modelled in the z-domain. The charge pump provides a proportionally damped signal, which is unlikely as a resistive or capacitive damping used in the conventional charge pump. The new damping results in a less update jitter and less peaking to achieve the lock frequency and fast locking time of the PLL. The new semi-digital PLL architecture uses $N$ storage cells. The $N$ storage cells is used to store the oscillator tuning information digitally and also enables analogue tuning of the voltage controlled oscillator (VCO). The storage cells outputs are also used for the process voltage temperature compensation. The phase-frequency detector (PFD) and VCO are implemented like a conventional PLL. The bandwidth achieved is 1/4th of the PFD update frequency for all over the operating range from 100~MHz to 1~GHz. The simulation results are also verified with the mathematical modelling. The new architecture also consumes less power and area compared to the conventional PLL.

This dissertation reports the development of a new multi-band multi-output synthesizer, 1/2 dual-injection locked divider, 1/3 injection-locked divider with phase-tuning, and 1/3 injection-locked divider with self-injection using 0.18-micrometer CMOS technology. The synthesizer is used for a multi-band multi-polarization radar system operating in the K- and Ka-band. The synthesizer is a fully integrated concurrent tri-band, tri-output phase-locked loop (PLL) with divide-by-3 injection locked frequency divider (ILFD). A new locking mechanism for the ILFD based on the gain control of the feedback amplifier is utilized to enable tunable and enhanced locking range which facilitates the attainment of stable locking states. The PLL has three concurrent multiband outputs: 3.47-4.313 GHz, 6.94-8.626 GHz and 19.44-21.42-GHz. High second-order harmonic suppression of 62.2 dBc is achieved without using a filter through optimization of the balance between the differential outputs. The proposed technique enables the use of an integer-N architecture for multi-band and microwave systems, while maintaining the benefit of the integer-N architecture; an optimal performance in area and power consumption. The 1/2 dual-ILFD with wide locking range and low-power consumption is analyzed and designed together with a divide-by-2 current mode logic (CML) divider. The 1/2 dual-ILFD enhances the locking range with low-power consumption through optimized load quality factor (QL) and output current amplitude (iOSC) simultaneously. The 1/2 dual-ILFD achieves a locking range of 692 MHz between 7.512 and 8.204 GHz. The new 1/2 dual-ILFD is especially attractive for microwave phase-locked loops and frequency synthesizers requiring low power and wide locking range. The 3.5-GHz divide-by-3 (1/3) ILFD consists of an internal 10.5-GHz Voltage Controlled Oscillator (VCO) functioning as an injection source, 1/3 ILFD core, and output inverter buffer. A phase tuner implemented on an asymmetric inductor is proposed to increase the locking range. The other divide-by-3 ILFD utilizes self-injection technique. The self-injection technique substantially enhances the locking range and phase noise, and reduces the minimum power of the injection signal needed for the 1/3 ILFD. The locking range is increased by 47.8 % and the phase noise is reduced by 14.77 dBc/Hz at 1-MHz offset.

Le déploiement à grande échelle de l’internet des objets nécessite le développement de systèmes de radiocommunication plus économes en énergie, dont le circuit de génération de fréquences est connu pour être particulièrement énergivore. L’objectif de ce travail de thèse est donc d’une part de développer une synthèse de fréquences très faible consommation et d’autre part de démontrer les performances de la technologie FDSOI pour des applications analogiques et radiofréquences. Dans le premier chapitre sont présentées les spécifications du standard choisi -le BLE-, les spécificités de la technologie FDSOI et l'état de l’art des architectures de transmetteurs radiofréquences à faible consommation. Nous avons retenue de cette comparaison l'architecture à division par phases. Le deuxième chapitre présente les résultats de trois types de modélisation système de l’architecture ; 1 - le fonctionnement de ses composants et les points clés à respecter pour son implémentation, 2 - le comportement en bruit de phase pour la définition des spécifications, et 3 - l’impact de l’architecture sur la génération de raies spectrales parasites. Cette étude nous a permis de fixer le cahier des charges du VCRO développé au chapitre suivant. Le troisième chapitre est consacré à la conception, la réalisation et le test de 4 topologies de VCROs en technologie FDSOI 28nm et d'un circuit de test. Les premiers résultats de mesure sont encourageants mais nécessitent d’être complétés par des mesures avec PLL fractionnaire intégrée. En effet, la sensibilité des circuits à la tension d’alimentation (pushing de l’ordre de 5 GHz/V) a rendu les mesures du bruit de phase très délicates. / The large-scale deployment of IoT requires the development of more efficient energy radio systems, within which the frequency generation circuit is known to be particularly energy-consuming. The objective of this thesis is firstly to develop a very low consumption frequency synthesis and secondly to demonstrate the performance of the FDSOI technology for analog and RF applications.In the first chapter are the specifications of the chosen standard -the BLE-, the specifications of the FDSOI technology and state of the art of low power radio frequency synthesizers architecture. We have chosen from this comparison the Fractional Phase Divider architecture. The second chapter presents the results of three types of system simulations of the PLL; 1 - the operation of its components and the key points to be respected for its implementation, 2 - the phase noise behavior for the definition of specifications, and 3 - the impact of architecture on the generation of spurious. This study allowed us to set the specifications of VCROs developed in the next chapter. The third chapter is dedicated to the design, implementation and testing of four topologies of VCROs and a test circuit in FDSOI 28nm technology. The first measurement results are encouraging but they need to be complemented by an integrated fractional PLL measurement. Indeed, the sensitivity of the circuits to the supply voltage (pushing of about 5 GHz/V) made measurements of phase noise very delicate. The measured consumption is less than 0.8 mA and the surface of the circuits is of the order of 600 µm².In the fourth and final chapter we present the implementation at circuit-level of a phase synchronization PLL.

abstract: Phase locked loops are an integral part of any electronic system that requires a clock signal and find use in a broad range of applications such as clock and data recovery circuits for high speed serial I/O and frequency synthesizers for RF transceivers and ADCs. Traditionally, PLLs have been primarily analog in nature and since the development of the charge pump PLL, they have almost exclusively been analog. Recently, however, much research has been focused on ADPLLs because of their scalability, flexibility and higher noise immunity. This research investigates some of the latest all-digital PLL architectures and discusses the qualities and tradeoffs of each. A highly flexible and scalable all-digital PLL based frequency synthesizer is implemented in 180 nm CMOS process. This implementation makes use of a binary phase detector, also commonly called a bang-bang phase detector, which has potential of use in high-speed, sub-micron processes due to the simplicity of the phase detector which can be implemented with a simple D flip flop. Due to the nonlinearity introduced by the phase detector, there are certain performance limitations. This architecture incorporates a separate frequency control loop which can alleviate some of these limitations, such as lock range and acquisition time. / Dissertation/Thesis / M.S. Electrical Engineering 2012

Since the creation of the system Navstar/GPS, several sources of observation errors went identified and studied by the scientific community, like as solution of ambiguities, delay ionospheric and non clock synchronous. The problem of the mistake caused by the multipath, however, persists as a challenge, especially for applications that demand larger accuracy and precision. In the case of Brazil, with the promulgation in 2001 of the Law 10267 of the National Cadaster of Rural Properties, this challenge have a specific feature, therefore it influences the applicability of the new cadastral system. The manufacturing companies of GPS receivers has been making great investments in research in that meaning, especially in level of project of receivers. This work analyses the applied technologies in two models of GPS receivers quite a lot used in the State of Rio Grande do Sul, BR, in other words, Ashtech Promark2 and Leica GS20, as well as to analyze the success of those technologies in level of representative field conditions of the reality of geodetic surveys in the State. The results show great potential of use of those receivers to certification works by Instituto Nacional de Colonização e Reforma Agrária (INCRA), as well as they evidences limit situations in that the employment of the same ones is not advised. / Desde a criação do sistema Navstar/GPS, várias fontes de erros nas observáveis foram sendo identificadas e estudadas pela comunidade científica, tais como a solução de ambigüidades, o atraso ionosférico e o não sincronismo de relógios. O problema do erro causado pelo multicaminho, no entanto, persiste como um desafio, especialmente para aplicações que exigem maior acurácia e precisão. No caso do Brasil, com a promulgação em 2001 da Lei 10267 que institui o Cadastro Nacional de Imóveis Rurais, este desafio passou a ter uma conotação específica, pois influencia a aplicabilidade do novo sistema cadastral. As empresas fabricantes de receptores GPS tem feito grandes investimentos em pesquisa nesse sentido, especialmente em nível de projeto dos seus receptores. A presente pesquisa busca estudar as tecnologias aplicadas em dois modelos de receptores GPS bastante utilizados no Estado do Rio Grande do Sul que são, o Ashtech Promark2 e o Leica GS20, bem como analisar o sucesso dessas tecnologias em nível de condições de campo representativas da realidade do georreferenciamento no Estado. Os resultados mostram grande potencial de uso desses receptores para trabalhos de certificação junto ao INCRA, bem como evidenciam situações limites em que o emprego dos mesmos fica prejudicado.

Les oscillateurs sont des blocs qui figurent dans presque tous les circuits. En effet,ils sont utilisés pour générer les signaux de synchronisation (les horloges), les signauxmodulés et démodulés ou récupérer des signaux noyés dans du bruit (détection synchrone).Les caractéristiques de ces oscillateurs dépendent de l'application. Dans le cas des boucles àverrouillage de phase (PLL), il existe de fortes exigences en matière de stabilité et de bruitde phase. En outre, face aux avancées des technologies nanométriques, il est égalementnécessaire de prendre en compte les effets liés à la variabilité des procédés de fabrication.Aujourd'hui, de nombreuses études sont menées sur les oscillateurs asynchrones en anneauqui présentent des caractéristiques bien adaptées à la gestion de la variabilité et qui offrentune structure appropriée pour limiter le bruit de phase. A ce titre, les anneaux asynchronessont considérés comme une solution prometteuse pour générer des horloges.Cette thèse étudie les avantages et les potentiels offerts par les oscillateursasynchrones en anneau. Deux applications principales ont été identifiées. D’une part, cesoscillateurs sont une solution prometteuse pour la génération d’horloges polyphasées àhaute fréquence et à faible bruit de phase. D’autre part, ils constituent une alternativesimple, dans une certaine mesure aux oscillateurs plus conventionnels et aux DLLs, car ilssont programmables en fréquence numériquement et sont susceptibles de fournir lesfonctionnalités d’arrêt de type gated clock de façon native. Plusieurs oscillateurs ont étéconçus, implémentés, fabriqués en technologie CMOS 65 nm de STMicroelectronics et,finalement, caractérisés sous pointes. Ces travaux ont notamment permis de démontrer lapertinence de ces oscillateurs, qui constituent une alternative sérieuse aux très classiquesoscillateurs en anneau à base d’inverseurs. / Oscillators are essential building blocks in many applications. For instance, they arebasic blocks in almost all designs: they are part of PLLs, clock recovery systems andfrequency synthesizers. The design of a low phase-noise multi-phase clock circuitry isespecially crucial when a large number of phases is required. There are plenty of workscovering the design of multiphase clocks. High frequency oscillators can be implementedusing ring structures, relaxation circuits or LC circuits. Ring architectures can easily providemultiple clocks with a small die size. With the advanced nanometric technologies, it is alsorequired to deal with the process variability, stability and phase noise. Today many studiesare oriented to Self-Timed Ring (STR) oscillators which present well-suited characteristicsfor managing process variability and offering an appropriate structure to limit the phasenoise. Therefore, self-timed rings are considered as promising solution for generatingclocks.This thesis studies the benefits and potential offered by Self-Timed Ring oscillators.Two main applications have been identified. On the one hand, these oscillators are apromising solution for the generation of high-frequency multi-phase low phase noise clocks.On the other hand, they are a simple alternative to some extent to the conventionaloscillators and DLLs, because they are digitally programmable. Several oscillators havebeen designed, implemented, manufactured in 65 nm CMOS technology fromSTMicroelectronics, and characterized. This work has demonstrated the relevance of theseoscillators, which are a serious alternative to the conventional ring oscillators based oninverters.

Les problématiques d'intégrabilité et de consommation des circuits sont au centre des spécifications des émetteurs pour la téléphonie mobile. L'architecture polaire est une alternative intéressante aux architectures cartésiennes pour réduire la consommation, la surface et la pollution de l'amplificateur de puissance (PA) sur la boucle à verrouillage de phase (PLL). Néanmoins, l'évolution des nouvelles normes de téléphonie mobile est allée de pair avec un élargissement de la bande passante des modulations, ce qui peut se montré critique pour l'architecture polaire. Les travaux de cette thèse se concentrent plus particulièrement sur le chemin de phase pour des modulations larges bandes, ce dernier étant moins étudié dans la littérature que le chemin d'amplitude par le PA. La modulation de phase large bande est réalisée directement par la PLL, qui reçoit en consigne à la fois le canal à adresser et la modulation qui est insérée en 2 points de la PLL. L'architecture de la PLL peut être analogique ou numérique. Grâce à des modèles événementiels développés sous Matlab, l'étude met en évidence certains phénomènes qui ne peuvent pas être observés par des modèles linéaires largement utilisés (Laplace, transformé en « z », …). L'étude identifie notamment, pour la PLL analogique, un phénomène de mélange du bruit avec la modulation dégradant fortement la qualité du signal. Ce travail propose une méthode de dimensionnement des filtres de modulation et de la fréquence de référence de la PLL pour résoudre ce problème. Pour la PLL numérique, un autre phénomène est identifié et amène à insérer la modulation en 3 points de la PLL. Finalement, une méthode de dimensionnement des banques de capacités dédiées à la modulation sur l'oscillateur est proposée. / Power consumption and integration are two key challenges of today mobile transmitter, especially for mobile phone applications. The polar architecture is an interesting alternative to classic architectures in order to reduce the power consumption, the silicon area and the pollution from the PA to the PLL. Unfortunately, the communication standards evolution such as LTE goes with a modulation bandwidth enlargement. This becomes critical for the use of polar architecture. Contrary to amplitude modulation done through the PA, phase modulation path through the PLL is less covered in literature. This phase modulation path which can be either analog or digital is the purpose of this work. Thanks to nonlinear event-driven models developed with Matlab, it has been possible to show some phenomenon which cannot be observed with widely used linear models (in Laplace or z-domain). For instance, in the fractional-N PLL, a mixing between the noise and the modulation signal strongly degrades the modulation performance. A method combining PLL sizing and modulation filtering is proposed to solve this issue. For the digital PLL, TDC gain estimation has a big impact on the EVM (Error Vector Magnitude) for wideband modulations and a solution is proposed which consists of converting the classical two-point modulator into a three-point modulator. Finally, an oscillator's capacitors banks sizing dedicated to the modulation is proposed.

A distribuição de sinais de tempo é um fator essencial em muitas aplicações de engenharia como, por exemplo, redes de telecomunicações, circuitos digitais integrados e sistemas de automação. Nas últimas décadas essa tarefa foi realizada, predominantemente, com redes mestre-escravo nas quais existem osciladores de referência que distribuem o sinal de tempo para osciladores escravos (PLLs) construídos para extrair a base de tempo a partir do sinal da linha. Recentemente, entretanto, o surgimento de redes de comunicação wire-less com conectividade dinâmica e o aumento dos tamanhos e das freqüências de operação dos circuitos digitais integrados indicam a necessidade de utilização de estratégias de distribuição de sinais de tempo baseadas em redes mutuamente conectadas. Nesse trabalho são estudadas redes mutuamente conectadas de PLLs para a determinação de condições para a obtenção do sincronismo de redes desse tipo em função dos parâmetros individuais dos nós e da conectividade da rede. Determinou-se também, através de simulações numéricas, a validade dos resultados analíticos obtidos. Finalmente foi estabelecido um método, baseado em algoritmos evolutivos, para a otimização dos parâmetros da rede considerando objetivos de robustez e capacidade de rejeição de ruídos na rede. / Clock-distribution is an essential feature in many engineering applications as, for example, telecommunications networks and digital integrated circuits. In the last few decades this problem was predominantly addressed using master-slave strategies. In this type of strategy there are precise reference oscillators in the network called masters and their signals are distributed in the network, other oscillators called slaves (PLLs) extract the time basis from the line signals. Recently the development of wireless communication networks and the increasing size of digital integrated circuits and their rising operation frequencies indicate the need for the use of mutually-connected networks for the issue of clock-distribution. In this work mutually-connected networks of PLLs are studied in order to obtain conditions for the acquisition of a synchronous state for the network concerning the node parameters and the connection pattern of the network. Furthermore, numerical experiments were conducted to validate analytic results. Finally, a method is proposed, based on evolutionary algorithms, for the optimization of the network parameters considering the robustness and the ability to reject noise in the network as objectives.

O presente trabalho propõe-se a oferecer respostas à questão de como a informação é preservada num sistema, focalizando-se na distinção entre os papéis desempenhados pelos constituintes elementares e pelos estruturais na preservação da memória desse sistema. Os sistema simulados circunscreveram-se a malhas, com diferentes graus de regularidade, compostas pelo acoplamento de osciladores não-lineares que apresentam comportamento coerente no estado de equilíbrio. Malhas de Sincronismo de Fase, também conhecidas por PLLs (Phase Locked Loops), foram adotadas como elementos constituintes básicos dos sistemas analisados. Para tanto, utilizou-se a plataforma de cálculo MATLAB-SIMULINK, acompanhando-se as evoluções dos diversos sistemas e de seus parâmetros dinâmicos associados, possibilitando o estabelecimento da correspondência entre os valores dos referidos parâmetros dinâmicos com parâmetros gráficos \"sensíveis\" à estrutura das malhas. Os resultados obtidos indicam a coexistência/cooperação das componentes estrutural e elementar na determinação dos valores dos parâmetros dinâmicos no estado de equilíbrio do sistema. No entanto, evidencia-se que tais componentes apresentam importâncias distintas na determinação dos diferentes parâmetros dinâmicos. / This work was conceived aiming to present some answers to how the information is preserved in a system. The focus was laid on the distinction between the tasks played by the elementary components and the structure of the system. The simulated systems were composed by coupled oscillators, more precisely by PLLs (Phase Locked Loops), arranged in networks of different regularities. Simulations were performed using Matlab-Simulink software to build a correlation between the final state dynamical parameters of the system and its degree of regularity. Results show the influence of both elementary and structural components on the system attained state. However the responses of characteristics parameters of the system to changes in the regularity of the structured network may greatly differ from one parameter to another. This behavior may suggest different strategies to preserve information of the system according to the information to be kept.

La demande croissante de toujours plus de débit pour les télécommunications entraine une augmentation de la fréquence de fonctionnement des liaisons séries. Cette demande se retrouve aussi dans les systèmes embarqués du fait de l'augmentation des performances des composants et périphériques. Afin de s'assurer que le train de données est bien réceptionné, un circuit de restitution d'horloge et de données est placé avant tout traitement du coté du récepteur. Dans ce contexte, les activités de recherche présentées dans cette thèse se concentrent sur la conception d'une CDR (Clock and Data Recovery). Nous détaillerons le comparateur de phase qui joue un rôle critique dans un tel système. Cette thèse présente un comparateur de phase ayant comme avantage d'avoir une mode de fenêtrage et une fréquence de fonctionnement réduite. La topologie spéciale utilisée pour la CDR est décrite, et la théorie relative aux oscillateurs verrouillés en injection est expliquée. L'essentiel du travail de recherche s'est concentrée sur la conception et le layout d'une restitution d'horloge dans le domaine millimétrique, à 80 Gbps. Pour cela plusieurs prototypes ont été réalisés en technologie BiCMOS 130 nm de STMicrolectronics. / The increasing bandwidth demand for telecommunication leads to an important rise of serial link operating frequencies. This demand is also present in embedded systems with the growth of devices and peripherals performances. To ensure the data stream is well recovered, a clock and data recovery (CDR) circuit is placed before any logical blocks on the receiver side. The research activities presented in this thesis are related to the design of such a CDR. The phase detector plays a critical role in the CDR circuit and is specially studied. This thesis presents a phase comparator that provides an enhancement by introducing a windowed mode and reducing its operating frequency. The used CDR has a special topology, which is described, and the injection locked oscillator theory is explained. Most of the research of this study has focused on the design and layout of a 80 Gbps CDR. Several prototypes are realized in 130 nm SiGe process from STMicroelectronics.