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International Telemetering Conference Proceedings / October 17-20, 1994 / Town & Country Hotel and Conference Center, San Diego, California / In this paper, a PCM telemetry system based on Personal computer is presented and some important methods that are used to realize the system will be introduced, such as a new kind of all digital PLL bit synchronizer and a way to solve the problem of high-rate data storage. The main idea of ours is to make the basic parts of PCM telemetry system (except receiver) in the form of PC cards compatible with EISA Bus, which forms a telemetry station with resource of PC computer. Finally, a laboratory prototype with rate up to 3.2Mbps is built.

Ingeniero Civil Eléctrico / Los sistemas de generación distribuida basados en fuentes renovables han experimentado un fuerte desarrollo a nivel mundial, con Alemania, Dinamarca, Japón y Estados Unidos como líderes en este campo. La sincronización de este tipo de fuentes a la red de suministro eléctrico es uno de los aspectos más importantes. La detección de la componente de secuencia positiva de la tensión a frecuencia fundamental es esencial para el control de la generación distribuida y de sistemas de almacenamiento. Considerando el contexto descrito, el objetivo general del presente trabajo es la elección de un algoritmo para la estimación de ángulo de fase en función del desempeño demostrado frente a distintas perturbaciones típicas de la red de distribución para su implementación en la Central Micro Hidráulica Plug & Play, correspondiente a un proyecto de desarrollo del Centro de Energía de la Universidad de Chile. Los métodos estudiados se basan en la técnica Phase Locked-Loop (PLL). La técnica PLL se puede definir como un método que permite la obtención de una señal de salida de igual frecuencia y fase a partir de una señal de entrada. El criterio de selección supone la simulación de distintos tipos de perturbaciones tales como distorsión armónica e interarmónica, alzas y caídas de tensión y saltos de frecuencia, entre otros. El funcionamiento de los algoritmos se prueba a nivel de simulación y a nivel experimental en la Central Micro Hidráulica Plug & Play con el fin de verificar su desempeño en condiciones reales de operación. Con el propósito de mejorar la respuesta dinámica de los algoritmos, se implementa, a nivel de simulación, una mejora del centro de frecuencia del esquema básico de PLL. De este modo se obtienen métodos que combinan un buen seguimiento de ángulo de fase y una buena velocidad de respuesta ante variaciones de la frecuencia de la red. Del trabajo realizado se desprende que las perturbaciones que combinan saltos de fase y desbalances de la magnitud de la tensión son más severas que aquellas que implican distorsión de la forma de onda o únicamente desbalances, los cuales se consideran menos graves; la diferencia entre el error de estimación en uno u otro caso puede ascender sobre los 5°. Los métodos de detección de ángulo de fase presentan un compromiso entre la dinámica y la precisión de seguimiento del ángulo de fase; dándose el caso de un error de estimación de 180° frente a saltos de frecuencia. Se concluye que los algoritmos basados en filtros presentan un mejor desempeño que aquellos basados en la componente de secuencia positiva de la tensión de la red de suministro, con diferencias entre sus errores de seguimiento acumulado de hasta 200 veces en el caso de sags de tensión y de hasta 6 veces frente a contenido armónico. El mejor método estudiado se basa en el uso de un observador y obtiene resultados ligeramente mejores que los presentados por los métodos basados en filtros. El conocimiento previo de las características del sistema es vital para la correcta sintonización de los métodos, pues determina el desempeño de los algoritmos. Se concluye que los métodos basados en PLL son una herramienta eficaz para la detección del ángulo de fase ante perturbaciones típicas de la red eléctrica de distribución. Adicionalmente, con el fin destacar más aún su utilidad, se simula el uso del PLL para la detección de operación en isla. Como trabajo futuro, entre otras cosas, se propone: la implementación experimental de centro de frecuencia variable y del mecanismo de detección de aislamiento, y la evaluación de los métodos frente a perturbaciones combinadas.

Submitted by PPG Engenharia El?trica (engenharia.pg.eletrica@pucrs.br) on 2018-01-16T12:25:22Z No. of bitstreams: 1 Dissertacao Henrique Cabral Final.pdf: 7113504 bytes, checksum: 991064508825d35b392d6e41b5e9023f (MD5) / Approved for entry into archive by Caroline Xavier (caroline.xavier@pucrs.br) on 2018-01-26T13:01:29Z (GMT) No. of bitstreams: 1 Dissertacao Henrique Cabral Final.pdf: 7113504 bytes, checksum: 991064508825d35b392d6e41b5e9023f (MD5) / Made available in DSpace on 2018-01-26T13:06:39Z (GMT). No. of bitstreams: 1 Dissertacao Henrique Cabral Final.pdf: 7113504 bytes, checksum: 991064508825d35b392d6e41b5e9023f (MD5) Previous issue date: 2016-08-29 / This work presents a study and a development of a current source microinverter, based on the ?uk converter operating in discontinuous conduction mode, for microgeneration purposes based on photovoltaic systems. In this sense, we carried out a steady-state analysis of the ?uk converter, in order to establish the design criteria for the ?uk microinverter. All peripheral systems required for the microinverter operation have also been developed, and are included in this study, namely: the MPPT, PLL, and islanding detection algorithms. All control systems, i.e., the MPPT, PLL, and anti-islanding detection algorithms, were implemented in the DS1104 R&D controller board, from dSPACE?, using MATLAB/Simulink? to program it. / Este trabalho apresenta o estudo e o desenvolvimento de um microinversor de corrente, baseado no conversor ?uk, operando no modo de condu??o descont?nua, para a aplica??o em microgera??o fotovoltaica. Inicialmente, s?o desenvolvidos estudos de car?ter qualitativo e quantitativo do comportamento do microinversor de corrente baseado no conversor ?uk, os quais culminaram no desenvolvimento de crit?rios para o dimensionamento do conversor ?uk, que desempenha um papel central na estrutura do microinversor proposto. Sistemas perif?ricos necess?rios para a opera??o do microinversor, assim como aqueles exigidos pelas concession?rias de energia el?trica para a aplica??o em sistemas de microgera??o s?o estudados e desenvolvidos nessa disserta??o. Para tanto, a implementa??o de todos os sistemas de controle, ou seja, os algoritmos de MPPT, de sincronismo, e de detec??o da opera??o ilhada, foram realizados em ambiente MATLAB/Simulink? associada ? uma placa de desenvolvimento do fabricante alem?o dSPACE?, modelo DS1104, a qual permite o controle em tempo real dos transistores do microinversor.

Le coût et le temps de test élevés des testeurs RadioFréquences (RF) poussent à l'optimisation de test, voir même à des méthodes alternatives de test pour les circuits analogiques-mixtes RF. Jusqu'à présent, le test des circuits RF était effectué par la validation des spécifications fonctionnelles du circuit. Cependant, à cause des contraintes imposées par les fréquences en jeu de plus en plus élevées et par des temps de test les plus réduits possible, la mesure de certaines spécifications fonctionnelles, même sur testeurs dédiés, n'est plus faisable. Il est ainsi nécessaire de développer de nouvelles méthodes de test permettant de répondre à ces besoins. Cette thèse a pour objectif de commencer le développement d'un bouquet des circuits de test sur puce de type BIST (Built-In Self Test) le plus général possible pour les circuits RF afin de supporter l'étape de conception et d'optimiser le test de production. La validation de ces circuits de BIST est orientée défaut. Le développement de la stratégie de validation d'un circuit de BIST se base sur les points suivants : choix des mesures de test avec simulation du circuit sous test ; modélisation des mesures de test et de spécifications du circuit sous test a travers simulations Monte-Carlo ; génération d'une population statistiquement plus représentative a travers la théorie des Copules ; génération d'une liste de fautes qui peuvent se produire dans le circuits sous test ; simulations d'injection de fautes ; analyse des métriques de test telles que le taux de couverture, le taux de circuits défaillants qui passent le test (defect level) et le rejet de circuits fonctionnels par le test (yield loss). Ces travaux ont été menés sur un cas d'étude industriel de type synthétiseur de fréquence, PLL (Phase-Locked Loop), conçu à STMicroelectronics.

<p> </p><p>As technique and requirement of today’s products keeps expending, Acreo AB has been researching for automotive radar that fulfills these requirements, e.g. higher resolution, faster system and lower cost.</p><p>The purpose of this master thesis work has been to evaluate a previous design and implement changes. The work has resulted in a PCB card that will be used to compare the performance between two radar modules. The demonstrator has been developed in two versions – first based on the existing GaAs-chipset (Gallium Arsenide) and a second with the inclusion of a low cost SiGe-chipset (Silicon Germanium).</p><p>The outcome of this work proves that some requirements cannot be fulfilled and therefore a next-generation radar demonstrator has been proposed. The new radar demonstrator includes changes that can fulfill the requirements.</p><p> </p>

<p>This is a thesis report done as part of the Master of Science in Electronics Design Engineering given at Linköping University, Campus Norrköping. The thesis work is done at Ericsson AB in the spring of 2005. The thesis describes a method of removing variations in the tuning sensitivity of voltage-controlled crystal oscillators due to different manufacturing processes. These variations results in unwanted variations in the modulation bandwidth of the phase-locked loop the oscillator is used in. Through examination of the theory of phase-locked loops it is found that the bandwidth of the loop is dependent on the tuning sensitivity of the oscillator.</p><p>A method of correcting the oscillator-sensitivity by amplifying or attenuating the control-voltage of the oscillator is developed. The size of the correction depends on the difference in oscillator-sensitivity compared to that of an ideal oscillator. This error is measured and the correct correction constant calculated.</p><p>To facilitate the measurements and correction extra circuits are developed and inserted in the loop. The circuits are both analog and digital. The analog circuits are mounted on an extra circuit board and the digital circuits are implemented in VHDL in an external FPGA.</p><p>Tests and theoretical calculations show that the method is valid and able to correct both positive and negative variations in oscillator-sensitivity of up to a factor ±2.5 times. The bandwidth of the loop can be adjusted between 2 to 15 Hz (up to ±8 dB, relative an unmodified loop).</p>

<p>Phase locked loop (PLLs) are the keystone for the electronic as well as for the communication circuits. Without any exaggeration, PLLs are found almost in every electronic and communication devices. Countless research has been performed, for the modification and enhancement of the PLLs circuit. While, due to the numerous advantage of the digital circuitry, the recent research is focusing on the all digital implementation of the PLLs. Therefore, it was competitive to touch with burning research.</p><p>Low power and wide range all digital phase locked loop (ADPLL), for video applications is presented. ADPLL has an operating input frequency between 10kHz to 150 kHz and output frequency between 10 MHz to 300 MHz. The phase frequency detector (PFD) is based on D-flip flops, having two output error and direction signal. The traditional charge pump (CP) is replaced by time-to-digital converters (TDC) and analog low pass filter (LPF) by digital low pass filter (digital-LPF). For completely digital architecture, voltage controlled oscillator (VCO) is replaced by the digitally controlled oscillator (DCO). In DCO, eleven bits are dedicated for controlling bits, two bits for biasing and one bit for enable the DCO. The designed steps for ADPLL were almost similar to the designed steps of a second order analog PLL. The ADPLL is implemented on a CMOS 65-nm technology.</p>

As technique and requirement of today’s products keeps expending, Acreo AB has been researching for automotive radar that fulfills these requirements, e.g. higher resolution, faster system and lower cost. The purpose of this master thesis work has been to evaluate a previous design and implement changes. The work has resulted in a PCB card that will be used to compare the performance between two radar modules. The demonstrator has been developed in two versions – first based on the existing GaAs-chipset (Gallium Arsenide) and a second with the inclusion of a low cost SiGe-chipset (Silicon Germanium). The outcome of this work proves that some requirements cannot be fulfilled and therefore a next-generation radar demonstrator has been proposed. The new radar demonstrator includes changes that can fulfill the requirements.

This is a thesis report done as part of the Master of Science in Electronics Design Engineering given at Linköping University, Campus Norrköping. The thesis work is done at Ericsson AB in the spring of 2005. The thesis describes a method of removing variations in the tuning sensitivity of voltage-controlled crystal oscillators due to different manufacturing processes. These variations results in unwanted variations in the modulation bandwidth of the phase-locked loop the oscillator is used in. Through examination of the theory of phase-locked loops it is found that the bandwidth of the loop is dependent on the tuning sensitivity of the oscillator. A method of correcting the oscillator-sensitivity by amplifying or attenuating the control-voltage of the oscillator is developed. The size of the correction depends on the difference in oscillator-sensitivity compared to that of an ideal oscillator. This error is measured and the correct correction constant calculated. To facilitate the measurements and correction extra circuits are developed and inserted in the loop. The circuits are both analog and digital. The analog circuits are mounted on an extra circuit board and the digital circuits are implemented in VHDL in an external FPGA. Tests and theoretical calculations show that the method is valid and able to correct both positive and negative variations in oscillator-sensitivity of up to a factor ±2.5 times. The bandwidth of the loop can be adjusted between 2 to 15 Hz (up to ±8 dB, relative an unmodified loop).