The viscosity and density of bis(8-methylnonyl) benzene-1,2- dicarboxylate {diisodecyl phthalate (DIDP)}, with a nominal viscosity at T = 298 K and p = 0.1 MPa of 87 mPa•s, have been measured at temperatures from (298.15 to 423.15) K and pressures from (0.1 to 70) MPa. A vibrating wire viscometer, with a wire diameter of about 0.15 mm, was utilised for the viscosity measurements and the results have an expanded uncertainty, (k = 2), including the error arising from the pressure measurement, of between ±(2 and 2.5) % The density was determined with two vibrating tube densimeters one for operation at p≈0.1 MPa with an expanded uncertainty (k = 2) of about ±0.1 %, the other that used at pressures up to 70 MPa, with an estimated expanded uncertainty (k = 2) of about ±0.3 %. Measurements of density and viscosity were performed on three samples of DIDP each with different purity stated by the supplier and as a function of water mass fraction. The measured viscosity and density are represented by interpolating expressions with differences between the experimental and calculated values that are comparable with the expanded (k = 2) uncertainties. The obtained viscosities at p = 0.1 MPa agree with values reported in the literature within the combined expanded (k = 2) uncertainties of the measurements while our densities differ by no more than 1.5 %. Viscosity data at p > 0.1 MPa deviate systematically from the literature values in the range of -10 % to 10 %. An apparatus capable of simultaneously measuring the solubility of a gas dissolved in a liquid and the viscosity and the density of the resulting mixture over a wide temperature and pressure range was constructed and tested. Preliminary results have been reported.

<p>Technological advancements in video technology have placed stringent requirements on video analog front ends (AFEs) to deliver high resolutions crisp images while consuming low power to deliver optimal performance.</p><p>One of the vital parts of an AFE is a delay locked loop (DLL). The DLL is a first order system that aligns  a delayed signal with respect to a reference signal while working in a feedback manner. DLLs find their applications in many electronic devices that deal with clocks in their operation. They are used to improve timing margins and clock delays in microprocessors, memory elements and other such applications. The vital function of a DLL is to delay the input clock (one period delay), by passing it through delay line and aligning the input clock and the delayed clock of the DLL through phase detector. Once this is done multiple phases canbe derived from various stages of the delay line with each providing a stable clock signal that is a delayed version of the input clock. Due to the increasing clock speeds this task of deriving multiple phases has become quite cumbersome. The task may become complicated due to noise generated from switching activity in digital circuits thus resulting in jitter at DLL output. As the design of analog circuits becomes quite exigent especially below the 100 nm mark, the goal hereis to design an all digital DLL to take advantage of the 65 nm process and a simplified design cycle.</p><p>The aim of this thesis is to implement an all digital delay locked loop with an input frequency range of 60 MHz to 300 MHz with a worst case jitter of 66 ps.The DLL provides 32 uniformly spaced phases between input and output clocks.The DLL operation is divided in to two stages. In the first step the first delayline quantizes input clock period with the help of a binary time to digital converter.Based on this quantization information second delay line introduces actual delay between input and output clocks with 32 intermediate phases in between.The entire process takes up to 9 clock cycles until a lock state is achieved. These 32 phases provide a greater phase resolution enhancing the sync processing characteristics of the video AFE thus improving the one screen display characteristics.</p>

<p>Phase locked loop (PLLs) are the keystone for the electronic as well as for the communication circuits. Without any exaggeration, PLLs are found almost in every electronic and communication devices. Countless research has been performed, for the modification and enhancement of the PLLs circuit. While, due to the numerous advantage of the digital circuitry, the recent research is focusing on the all digital implementation of the PLLs. Therefore, it was competitive to touch with burning research.</p><p>Low power and wide range all digital phase locked loop (ADPLL), for video applications is presented. ADPLL has an operating input frequency between 10kHz to 150 kHz and output frequency between 10 MHz to 300 MHz. The phase frequency detector (PFD) is based on D-flip flops, having two output error and direction signal. The traditional charge pump (CP) is replaced by time-to-digital converters (TDC) and analog low pass filter (LPF) by digital low pass filter (digital-LPF). For completely digital architecture, voltage controlled oscillator (VCO) is replaced by the digitally controlled oscillator (DCO). In DCO, eleven bits are dedicated for controlling bits, two bits for biasing and one bit for enable the DCO. The designed steps for ADPLL were almost similar to the designed steps of a second order analog PLL. The ADPLL is implemented on a CMOS 65-nm technology.</p>

The viscosity and density of bis(8-methylnonyl) benzene-1,2- dicarboxylate {diisodecyl phthalate (DIDP)}, with a nominal viscosity at T = 298 K and p = 0.1 MPa of 87 mPa•s, have been measured at temperatures from (298.15 to 423.15) K and pressures from (0.1 to 70) MPa. A vibrating wire viscometer, with a wire diameter of about 0.15 mm, was utilised for the viscosity measurements and the results have an expanded uncertainty, (k = 2), including the error arising from the pressure measurement, of between ±(2 and 2.5) % The density was determined with two vibrating tube densimeters one for operation at p≈0.1 MPa with an expanded uncertainty (k = 2) of about ±0.1 %, the other that used at pressures up to 70 MPa, with an estimated expanded uncertainty (k = 2) of about ±0.3 %. Measurements of density and viscosity were performed on three samples of DIDP each with different purity stated by the supplier and as a function of water mass fraction. The measured viscosity and density are represented by interpolating expressions with differences between the experimental and calculated values that are comparable with the expanded (k = 2) uncertainties. The obtained viscosities at p = 0.1 MPa agree with values reported in the literature within the combined expanded (k = 2) uncertainties of the measurements while our densities differ by no more than 1.5 %. Viscosity data at p > 0.1 MPa deviate systematically from the literature values in the range of -10 % to 10 %. An apparatus capable of simultaneously measuring the solubility of a gas dissolved in a liquid and the viscosity and the density of the resulting mixture over a wide temperature and pressure range was constructed and tested. Preliminary results have been reported.

The problem with which this study is concerned is establishing the relationship between scores on the Wechsler Intelligence Scale for Children-Revised (WISC-R) and the Wide Range Achievement Test (WRAT). The findings indicated a highly significant positive relationship between the WISC-R and WRAT, yielding a a < .001 for all rs between WISC-R Verbal, Performance, and Full Scale IQs and WRAT Reading, Spelling, and-Arithmetic. Analysis of WISC-R and WRAT subtests revealed slightly less significant relationships (a of at least .01) for all possible combinations. Results of this study indicate the possibility of using the WRAT Arithmetic score as a quick estimate of general level of achievement.

Thesis (M.A.)--University of Wisconsin--Madison, 1971. / eContent provider-neutral record in process. Description based on print version record. Includes bibliographical references.

Technological advancements in video technology have placed stringent requirements on video analog front ends (AFEs) to deliver high resolutions crisp images while consuming low power to deliver optimal performance. One of the vital parts of an AFE is a delay locked loop (DLL). The DLL is a first order system that aligns  a delayed signal with respect to a reference signal while working in a feedback manner. DLLs find their applications in many electronic devices that deal with clocks in their operation. They are used to improve timing margins and clock delays in microprocessors, memory elements and other such applications. The vital function of a DLL is to delay the input clock (one period delay), by passing it through delay line and aligning the input clock and the delayed clock of the DLL through phase detector. Once this is done multiple phases canbe derived from various stages of the delay line with each providing a stable clock signal that is a delayed version of the input clock. Due to the increasing clock speeds this task of deriving multiple phases has become quite cumbersome. The task may become complicated due to noise generated from switching activity in digital circuits thus resulting in jitter at DLL output. As the design of analog circuits becomes quite exigent especially below the 100 nm mark, the goal hereis to design an all digital DLL to take advantage of the 65 nm process and a simplified design cycle. The aim of this thesis is to implement an all digital delay locked loop with an input frequency range of 60 MHz to 300 MHz with a worst case jitter of 66 ps.The DLL provides 32 uniformly spaced phases between input and output clocks.The DLL operation is divided in to two stages. In the first step the first delayline quantizes input clock period with the help of a binary time to digital converter.Based on this quantization information second delay line introduces actual delay between input and output clocks with 32 intermediate phases in between.The entire process takes up to 9 clock cycles until a lock state is achieved. These 32 phases provide a greater phase resolution enhancing the sync processing characteristics of the video AFE thus improving the one screen display characteristics.

Phase locked loop (PLLs) are the keystone for the electronic as well as for the communication circuits. Without any exaggeration, PLLs are found almost in every electronic and communication devices. Countless research has been performed, for the modification and enhancement of the PLLs circuit. While, due to the numerous advantage of the digital circuitry, the recent research is focusing on the all digital implementation of the PLLs. Therefore, it was competitive to touch with burning research. Low power and wide range all digital phase locked loop (ADPLL), for video applications is presented. ADPLL has an operating input frequency between 10kHz to 150 kHz and output frequency between 10 MHz to 300 MHz. The phase frequency detector (PFD) is based on D-flip flops, having two output error and direction signal. The traditional charge pump (CP) is replaced by time-to-digital converters (TDC) and analog low pass filter (LPF) by digital low pass filter (digital-LPF). For completely digital architecture, voltage controlled oscillator (VCO) is replaced by the digitally controlled oscillator (DCO). In DCO, eleven bits are dedicated for controlling bits, two bits for biasing and one bit for enable the DCO. The designed steps for ADPLL were almost similar to the designed steps of a second order analog PLL. The ADPLL is implemented on a CMOS 65-nm technology.

The aim of the thesis was to propose a pump impeller with higher effectiveness and verify the proposal with the calculation using programs Gambit and Fluent. Three designed impellers were afterwards made using 3D printer and its characteristics were measured in a hydraulic laboratory in Kaplan Department of hydraulic machines. The proposal of a so called wideband impeller of the centrifugal pump was made with chaotic ordering of blade cascades, in one impeller occur blades with various input and output angles and different shapes of blades but all blades have got similar shape in a meridian sectional view of impeller. The thesis was divided into three parts. In the first part, a conforming transformation was theoretically described which was in the thesis used for the shape proposal of impeller blades. In the second part of the thesis final proposals and calculations of pump impellers were made. The third part of the thesis focused on the processing and evaluation of experimental measurement in the hydraulic laboratory and finally the results of the thesis were summarized in the conclusion.

No description available.