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  • About
  • The Global ETD Search service is a free service for researchers to find electronic theses and dissertations. This service is provided by the Networked Digital Library of Theses and Dissertations.
    Our metadata is collected from universities around the world. If you manage a university/consortium/country archive and want to be added, details can be found on the NDLTD website.
1

Programmable DLL-based Frequency Multiplier and A ROM-less Direct Digital Frequency Synthesizer

She, Hsien-Chih 25 June 2002 (has links)
This thesis includes two topics. The first topic is a programmable DLL-based frequency multiplier, which can be a local oscillator in RF applications. The second one is a ROM-less direct digital frequency synthesizer to serve as a good reference clock or to be used in digital modulation and demodulation. A CMOS local oscillator using a programmable DLL-based frequency multiplier is presented. In this work, low-Q on-chip inductors are not needed. The clock of the output frequency is digitally controllable, which is ranged from 7´ to 10´ of an input reference clock. The design is carried out by TSMC 1P5M 0.25 mm CMOS process at 2.5 V power supply. The output frequency range of the physical chips measurement is about 1.0 GHz ~ 1.5 GHz. Maximum power dissipation is 58.2 mW at 1.5 GHz output. A ROM-less direct digital frequency synthesizer (DDFS) employing trigonometric quadruple angle formula is presented. In a system-level simulation, the spurious tones performance is suppressed to be lower than -130 dBc. The resolution is up to 13 bits. The maximum error is also analyzed mathematically to meet the simulation results.
2

Desenvolvimento e implementação de um sintetizador de frequência CMOS utilizando sistema digital

Cardoso, Adriano dos Santos [UNESP] 25 November 2009 (has links) (PDF)
Made available in DSpace on 2014-06-11T19:30:32Z (GMT). No. of bitstreams: 0 Previous issue date: 2009-11-25Bitstream added on 2014-06-13T18:06:39Z : No. of bitstreams: 1 cardoso_as_dr_ilha.pdf: 731569 bytes, checksum: 5543d0ce31f156eb520e157b32344a2b (MD5) / Coordenação de Aperfeiçoamento de Pessoal de Nível Superior (CAPES) / Sintetizadores de frequência são circuitos críticos usados largamente em muitas aplicações de temporização. Circuitos PLL apresentam uma boa solução para temporização, mas utilizam geralmente blocos analógicos que são facilmente influenciados em desempenho devidos a instabilidades inerentes aos processos de fabricação e ruídos. Com a evolução dos circuitos e ferramentas para sistemas digitais foi possível a implementação de circuitos que utilizem somente recursos digitais tais como os DLL. Um dos papéis dos sintetizadores é equalizar a fase de um sinal de clock em relação a uma segunda referência adicionando fase entre os sinais. Este trabalho tem como objetivo o desenvolvimento de um circuito DLL com arquitetura flexível e programável para utilização no ajuste de fase e recuperação de sinais. Os blocos digitais foram implementados utilizando ferramentas de alto nível de abstração para avaliação do comportamento funcional. O objetivo final é a implementação do circuito validado em tecnologia CMOS 350 nm da AMS / Frequency Synthesizers are critical circuits widely used in timing applications. PLLs devices had showed a good solution for timing, but they normally because the use analog building blocks that are often influenced by the subtract building process and noises. Nevertheless, after the evolution of complex circuits and development tools it had been possible the implementation of systems that implement only digital resource such as DLL. One of major goals of synthesizers is to equalize the phase between a clock signal and a second reference. This work aims to develop DLL devices that are built in a flexible and reprogrammable architecture for using in decrements or increments in the phase and clock recovery. Digital blocks were implemented using high level abstraction tools for analysis of functional behavior. The main objective is the circuit implementation and validations in CMOS .35 AMS process
3

OPTIMIZATION OF REFERENCE WAVEFORM FILTERS IN COHERENT DELAY LOCKED LOOPS

Gunawardana, Upul, Kosbar, Kurt 10 1900 (has links)
International Telemetering Conference Proceedings / October 25-28, 1999 / Riviera Hotel and Convention Center, Las Vegas, Nevada / In this paper, a new coherent correlation-loop architecture for tracking direct-sequence spread-spectrum signals is proposed. In the proposed correlation loop model, the mean-square tracking error is minimized by varying the cross-correlation function between the received signal and the locally generated signal. The locally generated signal is produced by passing a replica of the transmitted signal through a linear time-invariant filter, which is termed the VCC filter. The issue of bandwidth of a correlation loop is addressed and a bandwidth definition for comparative purposes is introduced. The filter characteristics to minimize the tracking errors are determined using numerical optimization algorithms. This work demonstrates that the amplitude response of the VCC filter is a function of the input signal-to-noise ratio (SNR). In particular, the optimum filter does not replicate a differentiator at finite signal-to-noise ratio as is sometimes assumed. The optimal filter characteristics and the knowledge of the input SNR can be combined to produce a device that has very low probability of loosing lock.
4

Storage and retrieval technique for K-value estimation

Joag, Ela Pramod 14 February 2011 (has links)
Many chemical processes need large computation time to simulate. It has been observed that the speed of a process simulation depends to a large extent on evaluation of certain important functions in the system to be simulated. One such function is K-value estimation function which involves heavy vapor-liquid equilibrium calculations. Because of large number of K-value calculations, there can be a bottleneck in simulation convergence. Thus within process simulation applications computational speed is often emphasized and accuracy is compromised. In situ adaptive tabulation or ISAT, a storage and retrieval technique is proposed for speeding up K-value estimation in a process simulator (CHEMCAD®) using the input-output data. C language code is developed to implement ISAT algorithm for this application. The C code is then converted into Dynamic link library to be able to be used vii by main CHEMCAD® code as required. The overall testing with different K-value databases gave promising results improving computational time while maintaining accuracy. / text
5

Automating Malware Detection in Windows Memory Images using Machine Learning

Glendowne, Dae 09 May 2015 (has links)
Malicious software, or malware, is often employed as a tool to maintain access to previously compromised systems. It enables the intruders to utilize system resources, harvest legitimate credentials, and maintain a level of stealth throughout the process. During incident response, identifying systems infected with malware is necessary for effective remediation of an attack. When analysts lack sufficient indicators of compromise they are forced to conduct a comprehensive examination to identify anomalous behavior on a system, a time consuming and challenging task. Malware authors use several techniques to conceal malware on a system, with a common method being DLL injection. In this dissertation we present a system for automatically generating Windows 7 x86 memory images infected with malware, identifying the malicious DLLs injected into a process, and extracting the features associated with those DLLs. A set of 3,240 infected memory images was produced and analyzed to identify common characteristics of malicious DLLs in memory. From this analysis a feature set was constructed and two datasets were used to evaluate five classification algorithms. The ZeroR method was used as a baseline for comparison with accuracy and false positive rate (misclassifying malicious DLLs as legitimate) being the two metrics of interest. The results of the experiments showed that learning using the feature set is viable and that the performance of the classifiers can be further improved through the use of feature selection. Each of the classification methods outperformed the ZeroR method with the J48 Decision Tree obtaining the, overall, best results.
6

A PRECISÃO POSSÍVEL COM GPS L1-C/A EM GEORREFERENCIAMENTO: O DESAFIO DO MULTICAMINHO / THE POSSIBLE PRECISION WITH GPS L1-C/A IN GEODETIC SURVEYS: THE CHALLENGE OF THE MULTIPATH

Palma, Evandro 24 November 2005 (has links)
Since the creation of the system Navstar/GPS, several sources of observation errors went identified and studied by the scientific community, like as solution of ambiguities, delay ionospheric and non clock synchronous. The problem of the mistake caused by the multipath, however, persists as a challenge, especially for applications that demand larger accuracy and precision. In the case of Brazil, with the promulgation in 2001 of the Law 10267 of the National Cadaster of Rural Properties, this challenge have a specific feature, therefore it influences the applicability of the new cadastral system. The manufacturing companies of GPS receivers has been making great investments in research in that meaning, especially in level of project of receivers. This work analyses the applied technologies in two models of GPS receivers quite a lot used in the State of Rio Grande do Sul, BR, in other words, Ashtech Promark2 and Leica GS20, as well as to analyze the success of those technologies in level of representative field conditions of the reality of geodetic surveys in the State. The results show great potential of use of those receivers to certification works by Instituto Nacional de Colonização e Reforma Agrária (INCRA), as well as they evidences limit situations in that the employment of the same ones is not advised. / Desde a criação do sistema Navstar/GPS, várias fontes de erros nas observáveis foram sendo identificadas e estudadas pela comunidade científica, tais como a solução de ambigüidades, o atraso ionosférico e o não sincronismo de relógios. O problema do erro causado pelo multicaminho, no entanto, persiste como um desafio, especialmente para aplicações que exigem maior acurácia e precisão. No caso do Brasil, com a promulgação em 2001 da Lei 10267 que institui o Cadastro Nacional de Imóveis Rurais, este desafio passou a ter uma conotação específica, pois influencia a aplicabilidade do novo sistema cadastral. As empresas fabricantes de receptores GPS tem feito grandes investimentos em pesquisa nesse sentido, especialmente em nível de projeto dos seus receptores. A presente pesquisa busca estudar as tecnologias aplicadas em dois modelos de receptores GPS bastante utilizados no Estado do Rio Grande do Sul que são, o Ashtech Promark2 e o Leica GS20, bem como analisar o sucesso dessas tecnologias em nível de condições de campo representativas da realidade do georreferenciamento no Estado. Os resultados mostram grande potencial de uso desses receptores para trabalhos de certificação junto ao INCRA, bem como evidenciam situações limites em que o emprego dos mesmos fica prejudicado.
7

Ganttovy diagramy / Gantt charts

Kantar, Martin January 2014 (has links)
The thesis is aimed at Gantt charts. Primarily on their use in production processes, such as planning and scheduling. The thesis also includes an introduction, explaining what are the Gantt charts, for what are using and what is their principle. The thesis also includes analysis and software possibilities for implementing Gantt charts with using OOP. Programmatic and theoretical analysis of the various functions that are characteristic of Gantt charts, including their internal logic and program implementation. These programmed characteristic functions of Gantt charts were composed in the form of a DLL library, which provides a simple implementation of Gantt charts. By using this library is realized the software for production management. The work is included on the DVD, except the DLL itself software with detailed descriptions of each part of the source code.
8

Investigation and Implementation of a Live Connection between Configura CET and Revit Architecture 2009

Pintar, Freddie January 2009 (has links)
<p>Building Information Modeling -BIM- is an innovative method to seamlessly bridgecommunication within the architecture, engineering and construction industries.With BIM software you can exchange information during the design, construction,and maintaining. BIM can be seen as a continuation of the CAD software, wherethe users exchanged information by word of mouth, now is made automatically.To get the effect required for BIM one or more CAD-systems have to work togetherto exchange information. Revit Architecture is an application by Autodeskwhere BIM is used from the design and construction to the documentation andmaintaining of a building. Configura is one of the major software developers of interiorsolutions and want to integrate their software with Revit Architecture. Theconcept of objects in both software system suit well to be used in BIM and witha live connection these could be shared between the applications. One of the conclusionsin this investigation was that the only way to have integration betweenthe applications was to use the API provided by Autodesk. And therefore theimplementation is limited to the function in it. Revit API is a powerful programmingenvironment that let 3rd party software extend the functionality in Revit.The results show how Remote Procedure Call as a communication tool can beused to exchange data between the applications, how different type of data can berepresented in both applications, and why we cannot have a live synchronization.</p>
9

Intercepting OpenGL calls for rendering on 3D display

de Vahl, Joel January 2005 (has links)
<p>An OpenGL applications usually renders to a single frame. Multi-view or 3D displays on the other hand, needs more more images representing different viewing directions on the same scene, but modifying a large number of applications would be unsuitable and problematic. However, intercepting and modifying these calls before they reach the GPU would dramatically decrease the amount of work needed to support a large number of applications on a new type of multi-view or 3D display. This thesis describes different ways on intercepting, enqueueing and replaying these calls to support rendering form different view points. Intercepting with both an own implementation of opengl32.dll and an OpenGL driver is discussed, and enqueueing using classes, function pointers and enumeration of functions is tried. The different techniques are discussed quickly with the focus being a working implementation. This resulting in an fully blown OpenGL interceptor with the ability to enqueue and replay a frame multiple times while modifying parameters such as the projection matrix. This implementation uses an own implementation of opengl32.dll that is placed in the application directory to be loaded before the real one. Enqueueing is performed by enumerating all OpenGL calls, pushing this enumeration value and all call data to a list Replaying is done by reading the same list and calling the function pointer associated with the enumeration value with the data in the list.</p>
10

A Wide Range Low Power Low Jitter All Digital DLL for Video Applications / En heldigital, bredbandig DLL med lågt jitter och låg effektförbrukning förvideotillämpningar

Shah, Yasir Ali, Pasha, Muhammad Touqir January 2010 (has links)
<p>Technological advancements in video technology have placed stringent requirements on video analog front ends (AFEs) to deliver high resolutions crisp images while consuming low power to deliver optimal performance.</p><p>One of the vital parts of an AFE is a delay locked loop (DLL). The DLL is a first order system that aligns  a delayed signal with respect to a reference signal while working in a feedback manner. DLLs find their applications in many electronic devices that deal with clocks in their operation. They are used to improve timing margins and clock delays in microprocessors, memory elements and other such applications. The vital function of a DLL is to delay the input clock (one period delay), by passing it through delay line and aligning the input clock and the delayed clock of the DLL through phase detector. Once this is done multiple phases canbe derived from various stages of the delay line with each providing a stable clock signal that is a delayed version of the input clock. Due to the increasing clock speeds this task of deriving multiple phases has become quite cumbersome. The task may become complicated due to noise generated from switching activity in digital circuits thus resulting in jitter at DLL output. As the design of analog circuits becomes quite exigent especially below the 100 nm mark, the goal hereis to design an all digital DLL to take advantage of the 65 nm process and a simplified design cycle.</p><p>The aim of this thesis is to implement an all digital delay locked loop with an input frequency range of 60 MHz to 300 MHz with a worst case jitter of 66 ps.The DLL provides 32 uniformly spaced phases between input and output clocks.The DLL operation is divided in to two stages. In the first step the first delayline quantizes input clock period with the help of a binary time to digital converter.Based on this quantization information second delay line introduces actual delay between input and output clocks with 32 intermediate phases in between.The entire process takes up to 9 clock cycles until a lock state is achieved. These 32 phases provide a greater phase resolution enhancing the sync processing characteristics of the video AFE thus improving the one screen display characteristics.</p>

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