Thesis advisor: Zhifeng Ren / SiGe alloys are the only proven thermoelectric materials in power generation devices operating above 600 °C and up to 1000 °C in heat conversion into electricity using a radioisotope as the heat source. In addition to radioisotope applications, SiGe thermoelectric materials have many other potential applications, for example, solar thermal to electricity energy conversion and waste heat recovery. However, traditional SiGe alloy material shows low ZT values of about 0.93 at 900 °C, thus, 8% is the highest device efficiency for commercial SiGe thermoelectric devices. Recently, many efforts have been made to enhance the dimensionless thermoelectric figure-of-merit (ZT) of SiGe alloys. Among them, the nano approach has been recognized as an effective mechanism to obtain thermoelectric materials with good performance. In this approach, dense bulk samples with random nanostructures with high interface densities are synthesized through ball milling and a direct current hot press, leading to an enhancement ZT through reduced phonon thermal conductivity. Such a practical technique produced samples of nanostructured p-type dense bulk bismuth antimony telluride with a peak ZT of 1.4 at 1000 °C from either alloy ingot or elemental chunks. However, the generality of this approach has not been demonstrated. Here, we applied the same technique in SiGe system in order to fabricate a nanostructured n-type SiGe alloy with enhanced thermoelectric properties. In this thesis, numerous nanostructured n-type SiGe alloy samples were successfully pressed. The structure of these nanostructured samples was investigated via XRD, EDS, and TEM. It has been confirmed that many nano grains exist in our nanostructured samples. / Thesis (PhD) — Boston College, 2009. / Submitted to: Boston College. Graduate School of Arts and Sciences. / Discipline: Physics.

This work examines the effects of radiation and strain on silicon-germanium (SiGe) heterojunction bipolar transistor (HBT) BiCMOS technology. First, aspects of the various SiGe HBT BiCMOS technologies and the device physics of the SiGe HBT are discussed. The performance advantages of the SiGe HBT over the Si BJT are also presented. Chapter II offers a basic introduction to key radiation concepts. The space radiation environment as well as the two common radiation damage mechanisms are described. An overview of the effects of radiation damage on Si-based semiconductor devices, namely bipolar and CMOS, is also presented. Next, the effects of proton and gamma radiation on a new first-generation SiGe HBT technology are investigated. The results of a differential SiGe HBT LC oscillator subjected to proton irradiation are also presented as a test of circuit-level radiation tolerance. Finally, a technology comparison is made between the results of this work and the three different previously reported SiGe technologies. All reported SiGe HBT technologies to date show acceptable proton radiation tolerance up to Mrad levels. Chapter IV investigates the effects of effects of mechanical planar biaxial strain in SiGe HBT BiCMOS technology. This novel strain method is applied post fabrication, unlike many other straining methods. We report increases in the nFET saturated drain current, transconductance, and effective mobility for an applied strain of 0.123%. The pFET device performance degrades for this type of low-level strain.

Thermal properties of one dimensional nanostructures are of interest for thermoelectric energy conversion. Thermoelectric efficiency is related to non dimensional thermoelectric figure of merit, ZT=S^2 o T/k, where S ,o , k and T are Seebeck coefficient, electrical conductivity, thermal conductivity and the absolute temperature respectively. These physical properties are interdependent. Therefore, making materials with high ZT is a very challenging task. However, nanoscale materials can overcome some of these limitations. When the size of nanomaterials is comparable to wavelength and mean free path of energy carriers, especially phonons, size effect contributes to the thermal conductivity reduction without bringing about major changes in the electrical conductivity and the Seebeck coefficient. Therefore, the figure of merit ZT can be manipulated. For example, the thermal conductivities of several silicon nanowires were more than two orders of magnitude lower than that of bulk silicon values due to the enhanced boundary scattering. Among the nanoscale semiconductor materials, Silicon-Germanium(SiGe) alloy nanowire is a promising candidate for thermoelectric materials The thermal conductivities of SiGe core-shell nanowires with core diameters of 96nm, 129nm and 177nm were measured using a batch fabricated micro device in a temperature range of 40K-450K. SiGe nanowires used in the experiment were synthesized via the Vapour-Liquid-Solid (VLS) growth method. The thermal conductivity data was compared with thermal conductivity of Si and Ge nanowires. The data was compared with SiGe alloy thin film, bulk SiGe, Si/SixGe1-x superlattice nanowire, Si/Si0.7Ge0.3 superlattice thin film and also with the thermal conductivity of Si0.5Ge0.5 calculated using the Einstein model. The thermal conductivities of these SiGe alloy nanowires observed in this work are ~20 times lower than Si nanowires, ~10 times lower than Ge nanowires, ~3-4 times lower than Si/SixGe1-x superlattice thin film, Si/SixGe1-x superlattice nanowire and about 3 time lower than bulk SiGe alloy. The low values of thermal conductivity are majorly due to the effect of alloy scattering, due to increased boundary scattering as a result of nanoscale diameters, and the interface diffuse scattering by core-shell effect. The influence of core-shell effect, alloy scattering and boundary scattering effect in reducing the thermal conductivity of these nanowires opens up opportunities for tuning thermoelectric properties which can pave way to thermoelectric materials with high figures of merit in the future.

In order to improve the stability of interface between the solar cell (CuInSe2) and the substrate, such as reducing the lattice misfit and the number of defects at the interface, we used the Solid Phase Epitaxy (SPE) method to grow epitaxial germanium film as the substrate of solar cell. The experiment tried three different film structures. The first structure was sequential sputtering an amorphous silicon film and a germanium film on the silicon wafer. The next one was sputtering an amorphous germanium film on the bare silicon wafer. The last, called mixed step structure, was co-sputtering the amorphous silicon and germanium films by changing the sputtering power and time. After the recrystallization of amorphous films by rapid thermal process, x-ray diffraction patterns were performed to characterize the crystallinity of the processed films. The experimental results appeared that the epitaxy of amorphous films was not successful and that there was only polycrystalline films formed. TEM images of the processed amorphous films showed that there existed a thin native oxide layer at the interface between the silicon substrate and the polycrystalline films. The thin oxide layer (less than 10 nm) caused the epitaxy of amorphous films not to proceed.

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Dans le but d’améliorer les transistors bipolaires TBH SiGe, nous proposons d’étudier l’impact de la contrainte mécanique sur leurs performances. En effet, cette contrainte permet de libérer un degré de liberté supplémentaire pour améliorer les propriétés du transport grâce à un changement de la structure de bande d’énergie du semiconducteur. Ainsi, nous avons proposé de nouvelles architectures de composants basées sur l’ingénierie de la contrainte mécanique dans les semiconducteurs. Deux approches ont été utilisées dans cette étude pour générer la tension mécanique adéquate à l'intérieur du dispositif. La première approche consiste à appliquer une contrainte mécanique sur la base du transistor en utilisant une couche de SiGe extrinsèque. La seconde approche vise à appliquer une contrainte dans la région du collecteur en utilisant une couche contrainte. Les résultats obtenus montrent que cette méthode peut être une approche prometteuse pour améliorer les performances des TBH. / The Impact of strain engineering technology applied on Si BJT/SiGe HBT devices on the electrical properties and frequency response has been investigated. Strain technology can be used as an additional degree of freedom to enhance the carriers transport properties due to band structure changes and mobility enhancement. New concepts and novel device architectures that are based on strain engineering technology have been explored using TCAD modeling. Two approaches have been used in this study to generate the proper mechanical strain inside the device. The first approach was through introducing strain at the device’s base region using SiGe extrinsic stress layer. The second approach was through introducing strain at the device’s collector region using strain layers. The obtained results obviously show that strain engineering technology principle applied to BJT/HBT device can be a promising approach for further devices performance improvements.

Since metal-oxide-semiconductor (MOS) device was first reported around 1959 and utilized for integrated circuits in 1961, complementary MOS technology has become the mainstream of semiconductor industry. Its performance has been improved based on scaling of dimensions of MOS field-effect-transistors (MOSFET) in accordance with Moore’s law, which states that the density of MOSFETs due to scaling approximately doubles every two years. Entering into sub-100nm regime caused a lot of challenges. Traditional way of scaling no longer provided performance enhancement of individual MOSFETs. Increased channel doping which is required to prevent degradation of device electrostatics from short channel effects caused carrier mobility degradation. New inventions needed to be incorporated to sustain performance enhancement trend with scaling. Implementation of process induced strained Si technology allowed mobility enhancement, and high-K/metal gate instead of conventional poly-Si/SiO2 allowed continuing electrical gate oxide thickness scaling, hence extending the life span of Moore’s law. As we are now moving toward 22nm logic technology and below, new concerns have been rapidly aroused. Controlling power consumption and performance variability are becoming as important as developing scaled devices with enhanced performance. Expandability of strained-Si channel technology via process induced strain also faces increasing complexity from ever tighter gate pitch and difficulties in controlling defect level with the channel stress enhancement techniques. At the same time, long-lasting planar MOSFET architecture also faces serious challenges due to the limits of controlling short channel effects. New paradigms and pathways for future technology seems to be required. As a result, new material sets, new device architectures and concepts are being vigorously explored in the literature. These new trends can be categorized into three groups: MOSFET structure with (non-Si) high mobility channel materials, advanced (non-planar) MOSFET structures, and MOSFET-type structures with new device operation concepts such as tunneling FETs. This dissertation presents research on high mobility channel MOSFET structures (planar and non-planar) using group IV material (mainly SiGe) for enhanced performance and reduced operating power. This work especially focuses on improving the performance of short channel device performance of SiGe channel pMOSFETs which has long been researched yet clearly demonstrated in literature only recently. To reach the goal, novel processing technologies such as millisecond flash source/drain anneal and high pressure hydrogen post-metal anneal are explored. Finally, performance dependence on channel and substrate direction has been analyzed to find the optimal use of these SiGe channels. This work describes an exciting opportunity of weighting the possibility of using high mobility channel MOSFETs for future logic technology. / text

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Continued scaling of CMOS devices with Si and SixGe1-x down to 22 nm design node or beyond will require the formation of ever shallower and more abrupt junctions with higher doping levels in order to manage the short channel effects. With the increasing importance of surface proximity and stress effects, the lateral diffusion in gate-extension overlap region strongly influences both threshold voltage roll-off degradation and DIBL increase by requiring an optimized abruptness and diffusion for better device performance. Therefore, the detailed understanding of defect-dopant interactions in the disordered and/or strained systems is essential to develop a predictive kinetic model for the evolution of dopant concentration and electrical activation profiles. Our density functional theory calculations provide the guidance for experimental designs to realize ultra-shallow junction formation required for future generations of nano-scale CMOS devices. Few systematic studies in epitaxially-grown SixGe1-x channel CMOS have been reported. The physical mechanisms of boron diffusion in strained SixGe1-x/Si heterojunction layers with different SixGe1-x layer thicknesses and Ge content (>50%) are addressed, especially with high temperature annealing. In addition, the effects of the fluorine incorporated during BF2 implant on boron diffusion are investigated to provide more insight into short channel device design. In this study, we investigate how short channel margins are affected by Ge mole fraction and SixGe1-x layer thickness in a compressively strained SixGe1-x/Si heterojunction PMOS with high temperature annealing. Series resistance characterization in S/D extension region and gate oxide interface trap characterization for Si, SixGe1-x, and Ge nMOSFETs are done. TCAD device simulation is also performed to evaluate which distributions of interface traps will significantly affect the electrical characteristics such as flatband voltage (VFB) shift and threshold voltage (Vth) shift based on capacitance-voltage (CV) and current-voltage (IV) curves. n+/p and p+/n diode structures are studied in order to decouple the electrical characteristics from the gated-diode (GD) MOSFETs. With the extraction of S/D series resistance from various channel lengths, possible reasons for performance degradation in SixGe1-x and Ge nMOSFETs, based on simulations, are proposed. / text

Biaxial tensile strained Si grown on SiGe virtual substrates will be incorporated into future generations of CMOS technology due to the lack of performance increase with scaling. Compressively strained Ge-rich alloys with high hole mobilities can also be grown on relaxed SiGe. We review progress in strained Si and dual channel heterostructures, and also introduce high hole mobility digital alloy heterostructures. By optimizing growth conditions and understanding the physics of hole and electron transport in these devices, we have fabricated nearly symmetric mobility p- and n-MOSFETs on a common Si₀.₅Ge₀.₅ virtual substrate. / Singapore-MIT Alliance (SMA)