The objective of this work was to design high-speed circuits using silicon-germanium (SiGe) heterojunction bipolar transistors (HBTs) and complementary SiGe (C-SiGe) HBTs, as well as silicon (Si) complementary metal oxide semiconductor (CMOS) devices, for next-generation ultra-wideband (UWB) transceivers. The advantages of using UWB systems over conventional narrowband transceivers include their lower power requirements, higher data rate, more efficient spectrum usage, precise positioning capability, lower complexity, and lower cost. The two major components in a UWB transceiver IC are the radio frequency (RF) circuit and the analog-to-digital converter (ADC). In this work, circuit-level solutions to improve the speed and performance of critical building blocks in both the RF front-end and the ADC are presented. Device-related issues affecting SiGe HBTs for potential applications in UWB systems intended for use in extreme environments will also be investigated. This research envisions to realize various circuit blocks in a UWB transceiver including, a 3-10 GHz UWB low noise amplifiers (LNAs) in both the second (120 GHz) and third (200 GHz) SiGe technologies, an 8-bit 12 GSample/sec SiGe BiCMOS track-and-hold amplifier (THA), and a fifth order elliptic gm-c low-pass filter in C-SiGe HBT technology. This research will also focus on characterizing SiGe HBTs for UWB electronics for operation in extreme environments by investigating the proton radiation effects in the third generation SiGe HBTs.

Abstract In this thesis, we have fabricated a novel poly-Si thin film transistor with self-aligned SiGe raised source/drain (SiGe-RSD TFT). The SiGe-RSD regions were grown selectively by ultra-high vacuum chemical vapor deposition (UHVCVD) at 550¢J. The resultant transistor structure features a thin active channel region and a self-aligned thick source/drain region, which is ideally suited for optimum performance. A significant improvement on the turn-on current in the transfer characteristics is observed, compared to the conventional TFT counterpart. While the conventional TFT depicts severe resistance-limited output characteristics, especially at high gate bias, due to large source and drain series resistance. The new device, in contrast, exhibits excellent output characteristics. Finally, with comparable leakage current in both structures, the on/off current ratio is approximately 2 order of magnitudes higher in the proposed SiGe-RSD TFTS

The objective of the proposed research is to analyze the effects of total ionizing dose (TID) on highly scaled CMOS and Silicon-Germanium Heterojunction Bipolar Transistors (SiGE HBTs). TID damage is caused by a build-up of charge at sensitive Si-SiO₂ interfaces and may cause device or circuit failure. TID damage is due to an accumulation of radiation particle strikes seen in extreme environments, such as space.

Radiometers measures background radiation noise power of a target. The dominant quality factor of the radiometer is determined by how sensitive it is, so the lower the noise figure and the higher the gain, the more sensitive it is. It must also calibrate out any interfering noise such as sky background and system noise. Any change in gain of the radiometer receiver must also be taken into account. A Dicke radiometer compensates system gain and noise variation by switching between the target and a known noise source. To accomplish this, a single pole, double throw (SPDT) switch, switches between the receiving antenna and the noise source. The common terminal of the switch goes to the input of the low noise amplifier (LNA). This switch has a noise figure approximately equivalent to its loss and its noise is amplified by the LNA. To eliminate the loss of the switch, this paper studies a new approach of combining the switch and the LNA to become a “switchable” LNA by designing a two-stage gain block with the first stage capable of switching between the two inputs. Because the first stage is amplifying, there is no signal loss. This thesis investigates the new switching LNA and the design approach used in choosing the technology, the transistor size, biasing, extractions and matching. Two variations of the design were built using IBM’s SiGe 8HP 120nm process. The expected and measured results are compared. Results show a measured gain of 10dB and noise figure of 5dB at 19GHz. These results fall short of expectations for reasons explained in the thesis. The overall performance of this switching LNA is compared to the traditional methods. Performance criteria include gain, noise figure, isolation, matching and linearity vs. frequency and their stability vs. power and temperature variation. Power consumption, physical size and cost are also considered. The degree to which the two inputs track one another is discussed.

This research provides a method of using a mixed powder in tube approach for producing and characterizing large quantities of highly oriented, high aspect ratio semiconductor nanowires in an inherently safe and contained manner. This work modifies the previously used mixed powder method to produce significantly smaller features below 100nm in diameter. For the first time SiGe alloys are produced in optical fiber from a mixture of the two powders across the entire compositional range. A discussion of the properties of silicon and germanium and their alloys is given with emphasis on the differences between properties at the bulk scale and at the nanoscale. The limitations of silicon and germanium for photonic applications, due to their indirect band gap nature, is removed when these materials are reduced to the nanoscale. A brief discussion of ways that these properties can be modified is given with size, composition, and strain all being viable factors of control. The optical and electrical properties of these nanowire arrays is evaluated as a function of the size, number of wires, and composition. A clear dependence between size and quantity of wires was observed with respect to composition. The nanowires were found to have complex interactions with light showing high absorption as well as unique transmission characteristics. Arrays of these fibers were able to create a measurable photocurrent and provide potential uses for detection of light and other photonic applications. An understanding of the etching necessary to both expose these nanowires for analysis as well as completely remove them from the glass matrix was developed. Etch rates in these areas was observed to be higher than reported etch values. Etching with dilute solutions was found to allow removal of the wires cleanly and allow recovery of them for other applications. / Master of Science / This research provides a method of using a mixed powder in tube approach for producing and characterizing large quantities of highly oriented, high aspect ratio semiconductor nanowires in an inherently safe and contained manner. These wires are over 1000 times smaller than thickness of a human hair are made using traditional fiber drawing methods or pulling at high temperatures. These fibers differ from traditional optical fibers in that they are produced from a tube filled with powder instead of a solid glass rod. This is similar to the same method used to produce wires in other materials such as copper. The use of the glass to contain the semiconductor material allows us to increase the temperature it is pulled at above the melting point. The liquid material is then drawn into the very small sizes using pores in the glass powder it is mixed with. This allows these wires to be produced in much longer lengths, larger quantities, and easier than previous methods. These nanowires are produced from silicon and germanium, which are two of the most important materials currently used in electronics. These semiconductors are used in most electronics, solar cells, and LEDs that are used in everyday life. Silicon and germanium while very important materials have limitations in photonic applications, interactions with light. The properties of the materials for these applications can be improved by reducing them in size to the nanoscale. The wires produced in this research were evaluated to determine if they possessed the more ideal properties. The wires were found to have detectable photocurrent, electricity generated from light. This is the primary property that is needed in solar cells. The wires produced in this method are an important early step to improving solar cells efficiency and reliability. These v wires have benefits over other forms of silicon because they are produced with protective glass coating in a single step.

Les problématiques liées à la diminution de la taille des dispositifs actuels amènent l’industrie à réfléchir à des techniques de gravure ayant des résolutions à l’échelle de l’atome. Dans ce contexte, les techniques de nanostructuration directes sont très bien adaptées et représentent un potentiel important pour un futur proche dans les laboratoires de recherches. Le projet sur lequel j’ai travaillé avait pour but de coupler dans un environnement Ultra-Vide (UHV), un Dual-Beam, composé d’un FIB (Faisceau d’Ions Focalisé) et d’un MEB (Microscope électronique à balayage) et un bâti d’épitaxie par jet moléculaire (MBE), technique ultime en termes de dépôt. Cet environnement UHV répond à la nécessité de propreté absolue des substrats et constitue un moyen pertinent de rendre fonctionnels les dispositifs ainsi élaborés dans des domaines aussi variés que la micro-nanoélectronique, l’optoélectronique, le photovoltaïque, la spintronique, la plasmonique, etc. La connexion sous UHV de la nanofabrication FIB à la croissance MBE représente une voie unique pour fabriquer des structures 3D en alternant des étapes gravure/dépôt. Parmi les différentes applications, nous avons choisi de nous focaliser sur nanostructures de silicium. Le principal challenge pour l’industrie microélectronique et pour les chercheurs est d’être capable de réaliser une optoélectronique entièrement intégrée à base de Si. Cela nécessite de convertir les matériaux à base de Si en absorbeur/émetteur efficaces de lumière. Une des pistes les plus prometteuses pour obtenir une bande interdite directe est de combiner les effets de la fonctionnalisation chimique et du confinement quantique dans les nano-objets. / The reduction of device sizes represents a major issue in microelectronic industry which motivates several teams of researchers to develop nanopatterning with atomic resolution. In this context, maskless nanostructuration techniques are well-adapted and have an important potential for the nearest future in labs and industry. The aim of the project I worked on is the connection in a Ultra-High-Vacuum (UHV) environment between a Dual-Beam, equipped with a FIB (Focused Ion Beam) and a SEM (Scanning Electron Microscopy) and a MBE (Molecular Beam Epitaxy) cluster, which is the highest-controlled deposition technique. The UHV environment is the solution for an absolute cleanliness and represents a relevant way to fabricate functionalized devices for micro-nanoelectronics, optoelectronics, photovoltaic, spintronic, plasmonic, etc… This UHV connection combining FIB nanostructuration and epitaxy growth technique provides a unique platform to elaborate tridimensional structures with milling/deposition steps. Among different applications, we decided to focus on silicon based nanostructures. Regarding silicon nanostructures. The main challenge for microelectronics industry and for the researchers in this field is the realization of optoelectronics devices fully integrated in silicon systems. This requires to convert silicon based materials into absorber/emitter of light. One of the most promising way to change the electronic structure and to get a direct bandgap is the combination of chemical functionalization and quantum confinement into silicon based nano-objects.

Les materiaux à forte mobilité comme l’InGaAs et le SiGe sont considérés comme des candidats potentiels pour remplacer le Si dans les circuits CMOS futurs. De nombreux défis doivent être surmontés pour transformer ce concept en réalité industrielle. Cette thèse couvre les principaux challenges que sont l’intégration de l’InGaAs sur Si, la formation d’oxydes de grille de qualité, la réalisation de régions source/drain auto-alignées de faible résistance, l’architecture des transistors ou encore la co-intégration de ces matériaux dans un procédé de fabrication CMOS.Les solutions envisagées sont proposées en gardant comme ligne directrice l’applicabilité des méthodes pour une production de grande envergure.Le chapitre 2 aborde l’intégration d’InGaAs sur Si par deux méthodes différentes. Le chapitre3 détaille le développement de modules spécifiques à la fabrication de transistors auto-alignés sur InGaAs. Le chapitre 4 couvre la réalisation de différents types de transistors auto-alignés sur InGaAs dans le but d’améliorer leurs performances. Enfin, le chapitre 5 présente trois méthodes différentes pour réaliser des circuits hybrides CMOS à base d’InGaAs et de SiGe. / High-mobility channel materials such as indium-galium-arsenide (InGaAs) and silicon-germanium(SiGe) alloys are considered to be the leading candidates for replacing silicon (Si) in future lowpower complementary metal-oxide-semiconductor (CMOS) circuits. Numerous challenges haveto be tackled in order to turn the high-mobility CMOS concept into an industrial solution. Thisthesis addresses the majors challenges which are the integration of InGaAs on Si, the formationof high-quality gate stacks and self-aligned source and drain (S/D) regions, the optimizationof self-aligned transistors and the co-integration of InGaAs and SiGe into CMOS circuits. Allinvestigated possible solutions are proposed in the framework of very-large-scale integration requirements.Chapter 2 describes two different methods to integrate InGaAs on Si. Chapter 3 detailsthe developments of key process modules for the fabrication of self-aligned InGaAs metal-oxidesemiconductorfield-effect transistors (MOSFETs). Chapter 4 covers the realization of varioustypes of self-aligned MOSFETs towards the improvement of their performance. Finally, chapter5 demonstrates three different methods to make hybrid InGaAs/SiGe CMOS circuits.

Les technologies de films minces sur isolant apparaissent comme des solutions fiables pour la nano électronique. Elles permettent de dépasser les limites des technologies sur substrat silicium massif, en autorisant de faibles tensions d’utilisation et un gain en énergie significatif. En effet, les transistors à semi-conducteurs à grille métallique (MOSFET) avec un substrat totalement déplété (FDSOI) conduisent à des courants de fuites faible et améliorent la variabilité ce qui permet de diminuer les tensions d’alimentation en particulier pour les applications SRAM. A partir du nœud 14 nm, les transistors peuvent intégrer un canal SiGe, le diélectrique high-k et la grille métallique. Tous ces nouveaux modules de procédés technologiques rendent l’analyse électrique des transistors MOS ainsi que sa corrélation avec la technologie plus compliquées. Ce travail de thèse propose plusieurs nouvelles méthodologies d’extraction automatique et statistique de paramètres pour les empilements MOS FDSOI avancées. Ces méthodologies sont toutes basées sur des mesures de capacité par rapport à la tension (C-V) rendant compte du couplage capacitif entre grille métallique, canal et substrat face arrière. Avec de telles caractéristiques C-V, des méthodologies fiables sont proposées pour l’épaisseur d’oxyde de grille équivalente (EOT), le travail effectif de la grille métallique FDSOI (WFeff), ainsi que d’autres paramètres comme les épaisseurs du canal (tch) et de l’oxyde enterré (tbox) ainsi que l’affinité électronique efficace (Xeff) du substrat face arrière qui inclut les différents effets électrostatique à l’œuvre dans l’oxyde enterré et à ses interfaces. Ces différentes méthodologies ont été validées par des simulations quantiques. La force de l’analyse expérimentale a été de contrôler la cohérence des extractions obtenues sur tout un ensemble de transistors MOS obtenus à partir de variation sur les différentes briques de base et de contrôler la cohérence des paramètres extraits. / .Thin film technologies appear as reliable solutions for Nano electronics to go beyond bulk silicon technology limits, allowing lower power bias and thus energy harvesting. Indeed, Metal Oxide Semiconductors transistors (MOSFETs) with fully depleted substrate (FDSOI for ’Fully Depleted Silicon On Insulator’) allow low static off-currents and variability improvement that enable the use of power supply biases lower than with bulk silicon, especially for SRAMs. From 14nm nodes, FDSOI generations are including SiGe channel, high-k dielectric and metal gate. All these new process modules required for technology improvement also significantly increase the complexity of the MOS devices electrical analysis and meanwhile its correlation with technology. This PhD study propose different novel methodologies for automatic and statistical parameter extraction of advanced FDSOI MOS gate stack. These methodologies are all based on capacitance versus voltage (C-V) characteristics, obtained for the capacitive coupling between metal gate, channel and back side. With such C-V characteristics, reliable methodologies are proposed, leading to the extractions of the equivalent oxide thicknesses (EOT), the effective work function of the FDSOI metal gate (WFeff), but also other parameters such as channel and buried oxide thicknesses (tch, tbox) and an effective electron affinity of the substrate well (Xeff) that includes all electrostatic effects in the buried oxide and at its interfaces. Moreover, quantum simulations are considered in order to validate the different methodologies. For experimental analysis, the study has considered coherence and complementarity of different test structures as well as the impact of back substrate polarization

Les contraintes font maintenant partie des “ boosters ” de la microélectronique au même titre que le SOI (silicium sur isolant) ou le couple grille métallique / diélectrique haute permittivité. Appliquer une contrainte au niveau du canal des transistors MOSFETs (transistors à effet de champ à structure métal-oxyde-semiconducteur) permet d'augmenter de façon significative la mobilité des porteurs de charge. Il y a par conséquent un besoin de caractériser les déformations induites par ces contraintes à l'échelle nanométrique. L'holographie électronique en champ sombre est une technique de MET (Microscopie Électronique en Transmission) inventée en 2008 qui permet d'effectuer des cartographies quantitatives de déformation avec une résolution spatiale nanométrique et un champ de vue micrométrique. Dans cette thèse, la technique a été développée sur le microscope Titan du CEA. Différentes expériences ont été réalisées afin d'optimiser la préparation d'échantillon, les conditions d'illumination, d'acquisition et de reconstruction des hologrammes. La sensibilité et la justesse de mesure de la technique ont été évaluées en caractérisant des couches minces épitaxiées de Si_{1-x}Ge_{x}/Si et en effectuant des comparaisons avec des simulations mécaniques par éléments finis. Par la suite, la technique a été appliquée à la caractérisation de réseaux recuits de SiGe(C)/Si utilisés dans la conception de nouveaux transistors multi-canaux ou multi-fils. L'influence des phénomènes de relaxation, tels que l'interdiffusion du Ge et la formation des clusters de β-SiC a été étudiée. Enfin, l'holographie en champ sombre a été appliquée sur des transistors pMOS placés en déformation uniaxiale par des films stresseurs de SiN et des sources/drains de SiGe. Les mesures ont notamment permis de vérifier l'additivité des deux procédés de déformation. / Strain engineering is now considered as one of the most important boosters of microelectronics among other technologies such as SOI (Silicon On Insulator) and high-κ metal gates. By applying a stress in the channel of MOSFET (Metal Oxyde Semiconductor Field Effect Transistor) devices, the charge carriers mobility can be significantly increased. Consequently, there is now a need for a strain metrology at the nanometer scale. Dark-field electron holography is a TEM (Transmission Electron Microscopy) technique invented in 2008 that allows to map strain with micrometer field-of-view and nanometer spatial resolution. In this thesis, the technique was developed on the CEA Titan microscope. First, different developements were carried out concerning the sample preparation, the illumination/acquisition conditions and the reconstruction of the holograms. The sensitivity and the accuracy of the technique were evaluated through the characterization of Si_{1-x}Ge_{x} layers epitaxied on Si and by comparing the results with mechanical finite element simulations. Then, the technique was applied to the study of annealed SiGe(C)/Si superlattices that are used in the construction of new 3D architectures such as multichannel or multiwires transistors. The influence of the different relaxation mechanisms on the strain especially Ge interdiffusion and β-SiC clusters formation was investigated. Finally, dark-field electron holography was applied to the characterization of uniaxially strained pMOS transistors by SiN liners and recessed SiGe sources and drains. The measurements allowed to confirm the strain additivity of the two processes.

The terahertz (THz) and mid-infrared (MIR) spectral regions have many potential applications in the industrial, biomedical, and military sectors. Yet, a wide portion of this region of the electromagnetic spectrum (particularly the THz range) is still relatively unexplored, due mainly to the absence of suitable sources and photodetectors, related to the lack of practical semiconductor materials with adequately small band gap energies. Intersubband transitions (ISBTs) between quantized energy states in quantum heterostructures provide tunable wavelengths over a broad spectral range including the THz region, by choosing appropriate layer thicknesses and compositions. This work focuses on the development of THz and MIR Quantum Well Infrared Photodetectors (QWIPs) based on ISBTs in GaN/AlGaN and Si/SiGe heterostructures. Due to their large optical phonon energies, GaN materials allow extending the spectral reach of existing far-infrared photodetectors based on GaAs, and may enable higher-temperature operation. In the area of MIR optoelectronic devices, I have focused on developing QWIPs based on ISBTs in Si/SiGe heterostructures in the form of on strain-engineered nanomembranes. Due to their non-polar nature, these materials are free from reststrahlen absorption and ultrafast resonant electron/phonon scattering, unlike traditional III-V semiconductors. Therefore, Si/SiGe quantum wells (QWs) are also promising candidates for high-temperature high-performance ISB device operation (particularly in the THz region), with the additional advantage of direct integration with CMOS technology. In this thesis work, numerical modeling is used to design the active region of the proposed devices, followed by sample fabrication and characterization based on lock-in step-scan Fourier transform infrared spectroscopy. Three specific QWIP devices have been developed. The first is a III-nitride THz QWIP based on a novel double-step QW design in order to alleviate the material limitations provided by the intrinsic electric fields of GaN/AlGaN heterostructures. Next, I have developed a THz GaN/AlGaN QWIP grown on semi-polar (202 ̅1 ̅) GaN, where the detrimental effects of the internal fields are almost completely eliminated. Finally, I have demonstrated a Si/SiGe MIR QWIP based on a novel fabrication approach, where nanomembrane strain engineering is used to address the materials quality issues normally found in SiGe QWs. Promising photodetector performance is obtained in all cases. / 2017-06-21T00:00:00Z