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Semiconductor technology has already got into nanometer scale. As the dimension keeping scale down, we can get more transistor in the same area, and furthermore the frequency and performance are also enhanced. But nowadays the development of the lithography technology has come to the neck, we must find the other way to improve the performance of transistor. In this study, the strained silicon effect and reliability of CMOS are fully discussed. In order to get strain from the channel, silicon substrate is bent by applying external mechanical stress, the lattice of channel will have strain due to uniaxial tensile stress. By this way, we successfully improve drain current and mobility of NMOS into 12% and 6%, respectively. But there is no variation for PMOS. In addition, by DC stress, we can understand the hot carrier effect to strained silicon. In this work, both NMOS and PMOS present the same result, this is, as the silicon substrate is bent, the sharper of the curve, the worse of the reliability.

Biaxial tensile strained Si grown on SiGe virtual substrates will be incorporated into future generations of CMOS technology due to the lack of performance increase with scaling. Compressively strained Ge-rich alloys with high hole mobilities can also be grown on relaxed SiGe. We review progress in strained Si and dual channel heterostructures, and also introduce high hole mobility digital alloy heterostructures. By optimizing growth conditions and understanding the physics of hole and electron transport in these devices, we have fabricated nearly symmetric mobility p- and n-MOSFETs on a common Si₀.₅Ge₀.₅ virtual substrate. / Singapore-MIT Alliance (SMA)

In recent years, in order to promote the MOSFET¡¦s frequency and performance, the dimension keeping scale down, we can get more transistors in the same area. But nowadays the development of the lithography technology has come to the bottleneck, we must find the other way to improve the performance of transistor. In this study, the strained silicon effect and reliability of CMOS are fully discussed. In order to get strain from the channel, by process, deposit Si3N4 at NMOS and adopt the silicon-germanium epitaxy on source/drain by PMOS, can effective improve NMOS and PMOS electronic characteristic. Besides, silicon substrate is bent by applying external mechanical stress, the lattice of channel will have strain due to uniaxial tensile stress by NMOS and strain due to uniaxial compressive stress by PMOS. By these ways, we successfully improve drain current and mobility of NMOS and PMOS. Furthermore, this study is also probing into strain silicon at low temperature, the impacts on electronic characteristic by different scattering mechanism.

In this thesis, we investigate the electrical properties and reliability of novel metal-oxide-semiconductor field-effect transistors (MOSFETs) for 65 nm technology node and below. Roughly, we divide the thesis into two parts, strained-silicon channel engineering and high-k/metal gate stacks respectively. Firstly, to study the influence of stress on carrier transport properties, we proposed an approach to get uniaxial compressive/tensile stress from the channel by bending silicon substrate to enhance device performance. By applying uniaxial longitudinal tensile/compressive stress, the drain current and mobility were found to increase obviously in n/p-type MOSFETs, respectively. The enhancement can be attributed to the reduction of effective transport mass and to the suppression of inter-valley scattering. However, we found that the external mechanical stress aggravated hot carrier effects in n-type MOSFETs. Therefore, in n-type MOSFETs, the behaviors of the substrate current and the impact ionization rate under mechanical stress are investigated. It was found that the substrate current and gate voltage corresponding to the maximum impact ionization current has significantly increased by increasing external mechanical stress. According to the relationship to the strain-induced mobility enhancement, the increase in impact ionization efficiency resulted from the decrease in threshold energy for impact ionization which was due to the narrowing of the band gap. In p-type MOSFETs, the reliability issue, named negative bias temperature instability, is the dominant degradation mechanism during ON-state operation. Therefore, we investigate the NBTI characteristics of strained p-type MOSFETs with external uniaxial tensile/compressive stress. The results indicate that uniaxial compressive stress not only enhances drive current but also reduces NBTI degradation. On the contrary, uniaxial tensile stress leads to a significant degradation in both of drive current and NBTI behavior. The observed Cgc-Vg curve shows the inversion capacitance is strongly dependent on mechanical strain, meaning that the probability of electrochemical reaction decreases/or increases due to the changes in inversion carrier density according to the Nit generation rate of the reaction-diffusion model. Moreover, the charge pumping result is also consistent with the threshold voltage shift of the strained device, which means the degradation is mainly due to trap generation at the Si/SiO2 interface. In addition, to investigate the influences of biaxial compressive stress on p-MOSFETs, we attempts to combine intrinsic and external mechanical stress. It was found that drain current and hole mobility of p-type MOSFET with Si1-xGex raised Source/Drain and external applied mechanical stress significantly decreased due to the increase of effective conductive mass at room temperature. However, this phenomenon was inverted above 363K. Because hole can gain enough thermal energy to transit to higher energy level by inter-valley scattering, its transport mechanism was dominated by lower effective mass at higher energy level. Besides, the model is also evidenced that the mobility degradation under biaxial compressive stress becomes aggravated while temperature decreases from 300 K to 100 K, which is mainly due to the increase of the ratio of carriers occupied in lowest band. On the other hand, the SiO2 dielectric and poly-gate are unsuitable for CMOS application below 65 nm technology node due to unacceptable gate leakage current. Therefore, in the second section of this thesis, we established the electrical characteristics and physical mechanisms of MOSFETs with HfO2 dielectric/TiN gate by analyzing experimental data from charge pumping, split C-V, DC Id-Vg, and pulse Id-Vg. It is found that the threshold voltage (Vth) has a significant decrease as titanium increases in metal gate for n-MOSFETs, whereas the Vth increases in p-MOSFETs. By examining flat band voltage, we found the Vth shift was resulted from metal gate work function (£pm) which became smaller as titanium increased in metal gate. In addition,the dependence of effective mobility on temperature from 100K to 300K was entirely analyzed, which indicated HfO2 remote phonon scattering as the dominant cause of the mobility degradation in n- and p-type MOSFETs when titanium decreased. However, the gate leakage current is also strongly dependent on the nitrogen in metal gate. It is proved that the nitrogen can assivate the traps in HfO2 by pulse I-V,leading to the decrease in gate leakage dominated by Frenkel- Poole mechanism.

We have designed and constructed a novel Raman near-field scanning optical microscope (NSOM) and evaluated its performance characteristics with the goal of characterizing the strain in nanoscopic silicon structures. The Raman NSOM was built around a commercial Raman microscope to which a custom built stage was added to provide precise control over the tip position above the sample (z) using shear-force microscopy feedback as well as sample scanning in the x-y plane. The motion control axes were calibrated to better than 1 nm in z and approximately 20 nm in x and y. The NSOM provides both topographical images and Raman mapping with a lateral spectral resolution of 150-300 nm. The experiments described herein were enabled by gold-coated chemically etched NSOM tips with aperture diameters ranging between 60 and 150 nm. The sensitivity of the instrument was demonstrated by the high signal-to-noise ratios observed for Raman scattering by diamond and silicon in reflection mode. Spatial resolution and spectral sensitivity were demonstrated by obtaining well-resolved tip-sample separation curves that provide an accurate estimate of tip aperture size during an experiment. / text

abstract: The goal of this research work is to develop a particle-based device simulator for modeling strained silicon devices. Two separate modules had to be developed for that purpose: A generic bulk Monte Carlo simulation code which in the long-time limit solves the Boltzmann transport equation for electrons; and an extension to this code that solves for the bulk properties of strained silicon. One scattering table is needed for conventional silicon, whereas, because of the strain breaking the symmetry of the system, three scattering tables are needed for modeling strained silicon material. Simulation results for the average drift velocity and the average electron energy are in close agreement with published data. A Monte Carlo device simulation tool has also been employed to integrate the effects of self-heating into device simulation for Silicon on Insulator devices. The effects of different types of materials for buried oxide layers have been studied. Sapphire, Aluminum Nitride (AlN), Silicon dioxide (SiO2) and Diamond have been used as target materials of interest in the analysis and the effects of varying insulator layer thickness have also been investigated. It was observed that although AlN exhibits the best isothermal behavior, diamond is the best choice when thermal effects are accounted for. / Dissertation/Thesis / M.S. Electrical Engineering 2013

The semiconductor industry has decreased silicon-based device feature sizes dramatically over the last two decades for improved performance. However, current technology has approached the limit of achievable enhancement via this method. Therefore, other techniques, including introducing stress into the silicon structure, are being used to further advance device performance. While these methods produce successful results, there is not a proven reliable method for stress and strain measurements on the nanometer scale characteristic of these devices. The ability to correlate local strain values with processing parameters and device performance would allow for more rapid improvements and better process control. In this research, x-ray diffraction and convergent beam electron diffraction have been utilized to quantify the strain behavior of simple and complex strained silicon-based systems. While the stress relaxation caused by thinning of the strained structures to electron transparency complicates these measurements, it has been quantified and shows reasonable agreement with expected values. The relaxation values have been incorporated into the strain determination from relative shifts in the higher order Laue zone lines visible in convergent beam electron diffraction patterns. The local strain values determined using three incident electron beam directions with different degrees of tilt relative to the device structure have been compared and exhibit excellent agreement.

Metal-oxide-semiconductor field-effect transistors (MOSFETs) are major devices inintegrated circuit, extensively used in various electronic products. In order to improve the electrical characteristics, scaling channel width and length, using high-£e gate dielectric insulator, and strained silicon may be utilized to increase the driving current and circuit speed. Nevertheless, the scaling of the channel width and length must overcome the limitation of the photolithographytechnology and cost. Once the method is employed, the MOSFETs will face a serious short-channel effect and gate leakage current. In the aspect of high-£e gate dielectric insulator, there still have problems, containing the trap states, phonon scattering, dipole-induced threshold voltage variation, needed to be solved. This dissertation focuses on the properties of MOSFETs experienced an external-mechanical strain, where the channel will be strained. Hence, the mobility, driving current, and circuit speed will increase. Our research can be divided into three topics: fabricating process-induced strained Si, external mechanical stress-induced strained Si, and the properties of strained Si MOSFETs at different temperatures. Except the electrical measurement, we also used the ISE-TCAD to simulate the electrical characteristic of MOSFETs under stress. Firstly, we apply the stress on n-MOSFETs by utilizing the nitride-capping layer. Once the lattice is strained, the mobility will increase, hence resulting in the operating speed. Secondly, the electrical characteristics under external stress is explored by introduced the external mechanical stress along the channel length of nMOSFETs. In addition to the fabricating process-induced strain, the fabricating process condition will also influence the device characteristics. As a result, we propose a new strain technology for our following research. Thirdly, the device performance of strained Si under different temperatures is investigated. Finally, we discuss the gate leakage current in strained Si depending on the ultra-thin gate oxide layer.

Mit dem Erreichen der Grenzen der konventionellen MOSFET-Skalierung werden neue Techniken untersucht, um die Leistungsfähigkeit der CMOS-Technologie dem bisherigen Trend folgend weiter zu steigern. Einer dieser Ansätze ist die Verwendung mechanischer Verspannungen im Transistorkanal. Mechanische Verspannungen führen zu Kristalldeformationen und ändern die elektronische Bandstruktur von Silizium, so dass n- und p-MOSFETs mit verspannten Kanälen erhöhte Ladungsträgerbeweglichkeiten und demzufolge eine gesteigerte Leistungsfähigkeit aufweisen. Die vorliegende Arbeit beschäftigt sich mit den Auswirkungen mechanischer Verspannungen auf die elektronischen Eigenschaften planarer Silicon-On-Insulator-MOSFETs für Höchstleistungsanwendungen sowie mit deren Optimierung und technologischen Begrenzungen. Der Effekt der Verspannung auf die Bandstruktur von Silizium und die Ladungsträgerbeweglichkeit wird zunächst systematisch mit Hilfe der empirischen Pseudopotenzialmethode und der Deformationspotenzialtheorie untersucht. Verringerte Streuraten und kleinere effektive Massen als Folge der Aufspaltung der Energiebänder sowie von Bandverformungen sind der Hauptgrund für eine erhöhte Löcher- bzw. Elektronenbeweglichkeit. Die unterschiedlichen Konzepte zur Erzeugung der Verspannung werden kurz rekapituliert. Der Schwerpunkt der Untersuchungen liegt auf den verspannten Deckschichten, den Si1-xGex- bzw. Si1-yCy- Source/Drain-Gebieten, den verspannungsspeichernden Prozessen und den verspannten Substraten. Die starke Abhängigkeit dieser Verspannungstechniken von der Transistorstruktur macht die Nutzung numerischer Simulationen unabdingbar. So werden die Auswirkungen von Variationen der Transistorgeometrie sowie von Prozessparametern im Hinblick auf die Verspannung und die Drainstromänderungen der Transistoren neben den Messungen am gefertigten Transistor auch anhand numerischer Simulationen dargestellt und verglichen. Wesentliche Parameter für eine erhöhte Verspannung werden bestimmt und technologische Herausforderungen bei der Prozessintegration diskutiert. Die durchgeführten Simulationen und das erlangte Verständnis der Wirkungsweise der Verspannungstechniken ermöglichen es, das Potenzial dieser Verspannungstechniken für weitere Leistungssteigerungen in zukünftigen Technologiegenerationen abzuschätzen. Dadurch ist es möglich, die Prozessbedingungen und die Eigenschaften der fertigen Bauelemente im Hinblick auf eine gesteigerte Leistungsfähigkeit hin zu optimieren. Mit der weiteren Verkleinerung der Strukturgrößen der Bauelemente wird der zunehmende Einfluss der parasitären Source/Drain-Widerstände als Begrenzung der Effektivität der Verspannungstechniken identifiziert. Anschließend werden die Wechselwirkungen zwischen den einzelnen Verspannungstechniken hervorgehoben bzw. die gegebenenfalls auftretenden Einschränkungen angesprochen. Abschließend wird das Transportverhalten sowohl im linearen ohmschen Bereich als auch unter dem Einfluss hoher elektrischer Feldstärken analysiert und die deutlichen Unterschiede für die Leistungssteigerungen der verspannten n- und p-MOSFETs begründet. / As conventional MOSFET scaling is reaching its limits, several novel techniques are investigated to extend the CMOS roadmap. One of these techniques is the introduction of mechanical strain in the silicon transistor channel. Because strain changes the inter-atomic distances and thus the electronic band structure of silicon, ntype and p-type transistors with strained channels can show enhanced carrier mobility and performance. The purpose of this thesis is to analyze and understand the effects of strain on the electronic properties of planar silicon-on-insulator MOSFETs for high-performance applications as well as the optimization of various stress techniques and their technological limitations. First, the effect of strain on the electronic band structure of silicon and the carrier mobility is studied systematically using the empirical pseudopotential method and the deformation potential theory. Strain-induced energy band splitting and band deformations alter the electron and hole mobility through modulated effective masses and modified scattering rates. The various concepts for strain generation inside the transistor channel are reviewed. The focus of this work is on strained overlayer films, strained Si1-xGex and Si1-yCy in the source/drain regions, stress memorization techniques and strained substrates. It is shown, that strained silicon based improvements are highly sensitive to the device layout and geometry. For that reason, numerical simulations are indispensable to analyze the efficiency of the strain techniques to transfer strain into the channel. In close relation with experimental work the results from detailed simulation studies including parameter variations and material analyses are presented, as well as a thorough investigation of critical parameters to increase the strain in the transistor channel. Thus, the process conditions and the properties of the fabricated devices can be optimized with respect to higher performance. In addition, technological limitations are discussed and the potential of the different strain techniques for further performance enhancements in future technology generations is evaluated. With the continuing reduction in device dimensions the detrimental impact of the parasitic source/drain resistance on device performance is quantified and projected to be the bottleneck for strain-induced performance improvements. Next, the effects from a combination of individual strain techniques are studied and their interactions or possible restrictions are highlighted. Finally, the transport properties in the low-field transport regime as well as under high electrical fields are analyzed and the notable differences between strained n-type and p-type transistors are discussed.