PhD Thesis / Recently, gallium nitride high electron mobility transistor [GaN HEMT] has evolved as a promising device in the field of power electronics. It has excellent material qualities such as high bandgap, high saturation velocity, and good thermal stability which is expected to give superior device performances compared to its Si counterparts. One of the major challenges in GaN technology is to achieve enhancement operation (or normally off mode) due to the presence of its inherent two-dimensional electron gas[2DEG]. Among many methods developed to realize this, pGaN HEMT has emerged as the most encouraging technique for power GaN technology due to its high threshold voltage and good reliability. However, one of the major issues in pGaN HEMTs is that it suffers from high gate leakage current which limits their device performance. In this thesis, we have made a detailed study of the gate leakage process in pGaN HEMTs in terms of modeling, TCAD simulations, and alternative methods being used to reduce gate leakage in pGaN devices. A numerical model has been developed to model the gate leakage in pGaN HEMTs as a function of gate bias and temperature. This model is validated against 5 devices with different contact metals, geometries, and process conditions. A single model with a consistent set of parameters can fit the experimental data for all these 5 devices without the need to invoke multiple mechanisms to explain the gate leakage process. The numerical model relied on some simplifications, such as ignoring series resistance, using the compact diode model, and using a simplified expression to describe trap-assisted tunneling. Using commercial TCAD simulations, can address these limitations since the simulator computes the electric field distribution throughout the structure. Furthermore, using TCAD some of the trap levels have been identified which accounts for leakage at low bias. We were able to calibrate our TCAD simulations against published data for the drain current and then used the calibrated simulation environment to accurately simulate gate leakage using parameters that closely correspond to the physical phenomena described, including interface trap parameters, which we identify with known trap levels in GaN. Finally, we have examined different strategies that have been implemented so far to reduce leakage current. The pGaN layer is important in the whole device operation. Its doping concentration and thickness affect the leakage characteristics. Three modified structures have been studied through TCAD simulations which decrease gate leakage current. In each case, we used our calibrated TCAD model to study the impact on the drain current as well as the leakage current. Our results closely fit published experimental results and therefore provide confidence on the simulated dependence of leakage and drive current behavior on process modifications. The specific results, and our model overall, are expected to be of benefit to device designers in optimizing device structures for leakage while maintaining the required drive current. / Thesis / Doctor of Philosophy (PhD)

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Silicon Oxide/Oxynitride (SiO2/SiON) has been the mainstream material used for gate dielectric for MOS transistors for the past 30 years. The aggressive scaling of the feature size of MOS transistor has limited the ability of SiO2/SiON to work effectively as the gate dielectric to modulate the conduction of current of MOS transistors due to excess leakage current dominated by direct quantum tunneling. Due to this constraint, alternative gate dielectric/high-k is being employed to reduce the leakage current in order to maintain the rate of scaling of MOS transistors. However, the cost involved in the implementation of these new gate dielectric materials are high due to the requirements of a change in the process flow for device fabrication. This work presents the results of a novel processing method implementing the use of rapid thermal processing (RTP) on conventional SiO2/SiON gate dielectric to reduce the gate leakage current by three to five orders of magnitude. Electrical properties of the effect were characterized on fabricated MOS capacitors using semiconductor parameter analyzer and LCR meter. Material characterization was performed using FT-IR to understand the mechanism involved in this novel processing method, named PECE (Phonon-Energy-Coupling-Enhancement). By implementing this novel process, the use of SiO2/SiON as gate dielectric can be scaled further in conventional process flow of device fabrication.

In decades, the tremendous development of integrated circuits industry could be mostly attributed to SiO2, since its satisfactory properties as a gate dielectric candidate. The effectivity of SiO2 has been challenged since dielectric layer was scaled down below 3nm, when the gate leakage current of SiO2 became unacceptable. Institution to silicon-based CMOS techniques were proposed, but they have their own limitations. Nowadays, materials with high dielectric constants are mainstream gate dielectric materials in industry, but a SiO2 interfacial layer is still necessary to avoid gap between gate dielectric layer and Si substrate, and to minimize interface trap charges. In this thesis work, by applying lateral heating process on Si wafer with thermally grown ultrathin SiO2, the gate leakage current density could be reduced by 3-5 order of magnitude. MOS capacitors were fabricated, and electrical properties were tested with semiconductor parameter analyzer and LCR meter. The underlying mechanism of this appealing phenomenon was explored. Since unacceptable gate leakage current is one of the main reasons which prevent the scaling trend in semiconductor industry, this technology brings a possibility to post-pone the end of scaling trend, and pave a way for extensive application in industry. A new method for fabrication of MOS capacitors metal gate has been developed, and lift-off process has been replaced by wet etching process. This method provides better contact between dielectric layer and metal gate, meanwhile much easier operation.

The major sources of power dissipation in a nanometer CMOS circuit are capacitive switching, short-circuit current, static leakage and gate oxide tunneling. However, with the aggressive scaling of technology the gate oxide direct tunneling current (gate leakage) is emerging as a prominent component of power dissipation. For sub-65 nm CMOS technology where the gate oxide (SiO2) thickness is very low, the direct tunneling current is the major form of tunneling. There are two contribution parts in this thesis: analytical modeling of behavioral level components for direct tunneling current and propagation delay, and the reduction of tunneling current during behavioral synthesis. Gate oxides of multiple thicknesses are useful in reducing the gate leakage dissipation. Analytical models from first principles to calculate the tunneling current and the propagation delay of behavioral level components is presented, which are backed by BSIM4/5 models and SPICE simulations. These components are characterized for 45 nm technology and an algorithm is provided for scheduling of datapath operations such that the overall tunneling current dissipation of a datapath circuit under design is minimal. It is observed that the oxide thickness that is being considered is very low it may not remain constant during the course of fabrication. Hence the algorithm takes process variation into consideration. Extensive experiments are conducted for various behavioral level benchmarks under various constraints and observed significant reductions, as high as 75.3% (with an average of 64.3%).

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Metal-oxide-semiconductor field-effect transistors (MOSFETs) are major devices inintegrated circuit, extensively used in various electronic products. In order to improve the electrical characteristics, scaling channel width and length, using high-£e gate dielectric insulator, and strained silicon may be utilized to increase the driving current and circuit speed. Nevertheless, the scaling of the channel width and length must overcome the limitation of the photolithographytechnology and cost. Once the method is employed, the MOSFETs will face a serious short-channel effect and gate leakage current. In the aspect of high-£e gate dielectric insulator, there still have problems, containing the trap states, phonon scattering, dipole-induced threshold voltage variation, needed to be solved. This dissertation focuses on the properties of MOSFETs experienced an external-mechanical strain, where the channel will be strained. Hence, the mobility, driving current, and circuit speed will increase. Our research can be divided into three topics: fabricating process-induced strained Si, external mechanical stress-induced strained Si, and the properties of strained Si MOSFETs at different temperatures. Except the electrical measurement, we also used the ISE-TCAD to simulate the electrical characteristic of MOSFETs under stress. Firstly, we apply the stress on n-MOSFETs by utilizing the nitride-capping layer. Once the lattice is strained, the mobility will increase, hence resulting in the operating speed. Secondly, the electrical characteristics under external stress is explored by introduced the external mechanical stress along the channel length of nMOSFETs. In addition to the fabricating process-induced strain, the fabricating process condition will also influence the device characteristics. As a result, we propose a new strain technology for our following research. Thirdly, the device performance of strained Si under different temperatures is investigated. Finally, we discuss the gate leakage current in strained Si depending on the ultra-thin gate oxide layer.

The progress of the silicon-based complementary-metal-oxide-semiconductor (CMOS) technology is mainly contributed to the scaling of the individual component. After decades of development, the scaling trend is approaching to its limitation, and there is urgent needs for the innovations of the materials and structures of the MOS devices, in order to postpone the end of the scaling. Atomic layer deposition (ALD) provides precise control of the deposited thin film at the atomic scale, and has wide application not only in the MOS technology, but also in other nanostructures. In this dissertation, I study rapid thermal processing (RTP) treatment of thermally grown SiO2, ALD growth of SiO2, and ALD growth of high-k HfO2 dielectric materials for gate oxides of MOS devices. Using a lateral heating treatment of SiO2, the gate leakage current of SiO2 based MOS capacitors was reduced by 4 order of magnitude, and the underlying mechanism was studied. Ultrathin SiO2 films were grown by ALD, and the electrical properties of the films and the SiO2/Si interface were extensively studied. High quality HfO2 films were grown using ALD on a chemical oxide. The dependence of interfacial quality on the thickness of the chemical oxide was studied. Finally I studied growth of HfO2 on two innovative interfacial layers, an interfacial layer grown by in-situ ALD ozone/water cycle exposure and an interfacial layer of etched thermal and RTP SiO2. The effectiveness of growth of high-quality HfO2 using the two interfacial layers are comparable to that of the chemical oxide. The interfacial properties are studied in details using XPS and ellipsometry.

With the MOSFET scaling practice, the performance of IC devices is improved tremendously as we experienced in the last decades. However, the small semiconductor devices also bring some drawbacks among which the high gate leakage current is becoming increasingly serious. This thesis work is focused on the of gate leakage current reduction in thin oxide semiconductor devices. The method being studied is the Phonon Energy Coupling Enhancement (PECE) effect induced by Rapid Thermal Processing (RTP). The basic MOS capacitors are used to check improvements of leakage current reduction after appropriate RTP process. Through sets of experiments, it is found that after RTP in Helium environment could bring about four orders reduction in gate leakage current of MOS capacitors.

Aggressive scaling of CMOS circuits in recent times has lead to dramatic increase in leakage currents. Previously, sub-threshold leakage current was the only leakage current taken into account in power estimation. But now gate leakage and reverse biased junction band-to-band-tunneling leakage currents have also become significant. Together all the three types of leakages namely sub-threshold leakage, gate leakage and reverse bias junction band-to-band tunneling leakage currents contribute to more than 25% of power consumption in the current generation of leading edge designs. Different sources of leakage can affect each other by interacting through resultant intermediate node voltages. This is called loading effect and it leads to further increase in leakage current. On the other hand, sub-threshold leakage current decreases as more number of transistors is stacked in series. This is called stack effect. Previous works have been done that analyze each type of leakage current and its effect in detail but independent of each other. In this work, a pattern dependent steady state leakage estimation technique was developed that incorporates loading effect and accounts for all three major leakage components, namely the gate leakage, band to band tunneling leakage and sub-threshold leakage. It also considers transistor stack effect when estimating sub-threshold leakage. As a result, a coherent leakage current estimator tool was developed. The estimation technique was implemented on 65nm and 45nm CMOS circuits and was shown to attain a speed up of more than 10,000X compared to HSPICE. This work also extends the leakage current estimation technique in Field Programmable Gate Arrays (FPGAs). A different version of the leakage estimator tool was developed and incorporated into the Versatile Place & Route CAD tool to enable leakage estimation of design after placement and routing. Leakage current is highly dependent on the steady state terminal voltage of the transistor, which depends on the logic state of the CMOS circuit as determined by the input pattern. Consequently, there exists a pattern that will produce the highest leakage current. This work considers all leakage sources together and tries to find an input pattern(s) that will maximize the composite leakage current made up of all three components. This work also analyzes leakage power in presence of dynamic power in a unique way. Current method of estimating total power is to sum dynamic power which is ½&#;CLVDD2f and sub-threshold leakage power. The dynamic power in this case is probabilistic and pattern independent. On the other hand sub-threshold leakage is pattern dependent. This makes the current method very inaccurate for calculating total power. In this work, it is shown that leakage current can vary by more than 8% in time in presence of switching current.