Aggressive scaling of CMOS circuits in recent times has lead to dramatic increase in leakage currents. Previously, sub-threshold leakage current was the only leakage current taken into account in power estimation. But now gate leakage and reverse biased junction band-to-band-tunneling leakage currents have also become significant. Together all the three types of leakages namely sub-threshold leakage, gate leakage and reverse bias junction band-to-band tunneling leakage currents contribute to more than 25% of power consumption in the current generation of leading edge designs. Different sources of leakage can affect each other by interacting through resultant intermediate node voltages. This is called loading effect and it leads to further increase in leakage current. On the other hand, sub-threshold leakage current decreases as more number of transistors is stacked in series. This is called stack effect. Previous works have been done that analyze each type of leakage current and its effect in detail but independent of each other. In this work, a pattern dependent steady state leakage estimation technique was developed that incorporates loading effect and accounts for all three major leakage components, namely the gate leakage, band to band tunneling leakage and sub-threshold leakage. It also considers transistor stack effect when estimating sub-threshold leakage. As a result, a coherent leakage current estimator tool was developed. The estimation technique was implemented on 65nm and 45nm CMOS circuits and was shown to attain a speed up of more than 10,000X compared to HSPICE. This work also extends the leakage current estimation technique in Field Programmable Gate Arrays (FPGAs). A different version of the leakage estimator tool was developed and incorporated into the Versatile Place & Route CAD tool to enable leakage estimation of design after placement and routing. Leakage current is highly dependent on the steady state terminal voltage of the transistor, which depends on the logic state of the CMOS circuit as determined by the input pattern. Consequently, there exists a pattern that will produce the highest leakage current. This work considers all leakage sources together and tries to find an input pattern(s) that will maximize the composite leakage current made up of all three components. This work also analyzes leakage power in presence of dynamic power in a unique way. Current method of estimating total power is to sum dynamic power which is ½&#;CLVDD2f and sub-threshold leakage power. The dynamic power in this case is probabilistic and pattern independent. On the other hand sub-threshold leakage is pattern dependent. This makes the current method very inaccurate for calculating total power. In this work, it is shown that leakage current can vary by more than 8% in time in presence of switching current.

<p>Heteroepitaxial SiGeC layers have attracted immenseattention as a material for high frequency devices duringrecent years. The unique properties of integrating carbon inSiGe are the additional freedom for strain and bandgapengineering as well as allowing more aggressive device designdue to the potential for increased thermal budget duringprocessing. This work presents different issues on epitaxialgrowth, defect density, dopant incorporation and electricalproperties of SiGeC epitaxial layers, intended for variousdevice applications.</p><p>Non-selective and selective epitaxial growth of Si_1-x-yGe_xC_y(0≤x≤30, ≤y≤0.02) layershave been optimized by using high-resolution x-ray reciprocallattice mapping. The incorporation of carbon into the SiGematrix was shown to be strongly sensitive to the growthparameters. As a consequence, a much smaller epitaxial processwindow compared to SiGe epitaxy was obtained. Differentsolutions to decrease the substrate pattern dependency (loadingeffect) of SiGeC growth have also been proposed. The key pointin these methods is based on reduction of surface migration ofthe adsorbed species on the oxide. In non-selective epitaxy,this was achieved by introducing a thin silicon polycrystallineseed layer on the oxide. The thickness of this seed layer had acrucial role on both the global and local loading effect, andon the epitaxial quality. Meanwhile, in selective epitaxy,polycrystalline stripes introduced around the oxide openingsact as migration barriers and reduce the loading effecteffectively. Chemical mechanical polishing (CMP) was performedto remove the polycrystalline stripes on the oxide.</p><p>Incorporation and electrical properties of boron-doped Si_1-x-yGe_xC_ylayers (x=0.23 and 0.28 with y=0 and 0.005) with aboron concentration in the range of 3x10¹⁸-1x10²¹atoms/cm3 have also been investigated. In SiGeClayers, the active boron concentration was obtained from thestrain compensation. It was also found that the boron atomshave a tendency to locate at substitutional sites morepreferentially compared to carbon. These findings led to anestimation of the Hall scattering factor of the SiGeC layers,which showed good agreement with theoretical calculations.</p><p><b>Keywords:</b>Silicon germanium carbon (SiGeC), Epitaxy,Chemical vapor deposition (CVD), Loading effect, Highresolution x-ray diffraction (HRXRD), Hall measurements, Atomicforce microscopy (AFM).</p>

This thesis deals with the main aspects in chemical vapordeposition (CVD) of silicon (Si) and silicon-germanium (Si1-xGex) films for high-speed bipolar transistors.In situdoping of polycrystalline silicon (poly-Si)using phosphine (PH3) and disilane (Si2H6) in a low-pressure CVD reactor was investigated toestablish a poly-Si emitter fabrication process. The growthkinetics and P incorporation was studied for amorphous Si filmgrowth. Hydrogen (H) incorporated in the as-deposited films wasrelated to growth kinetics and the energy for H2desorption was extracted. Film properties such asresistivity, mobility, carrier concentration and grain growthwere studied after crystallization using either furnaceannealing or rapid thermal annealing (RTA). In order tointegrate an epitaxial base, non-selective epitaxial growth(NSEG) of Si and SiGe in a lamp-heated single-waferreduced-pressure CVD reactor was examined. The growth kineticsfor Si epitaxy and poly-Si deposition showed a differentdependence on the deposition conditions i.e. temperature andpressure. The growth rate difference was mainly due to growthkinetics rather than wafer surface emissivity effects. However,it was observed that the growth rate for Si epitaxy and poly-Sideposition was varying during growth and the time-dependencewas attributed to wafer surface emissivity variations. A modelto describe the emissivity effects was established, taking intoconsideration kinetics and the reactor heating mechanisms suchas heat absorption, emission andconduction. Growth ratevariations in opening of different sizes (local loading) andfor different oxide surface coverage (global loading) wereinvestigated. No local loading effects were observed, whileglobal loading effects were attributed to chemical as well astemperature effects. Finally, misfit dislocations formed in theSiGe epitaxy during NSEG were found to originate from theinterface between the epitaxial and polycrystalline regions.The dislocations tended to propagate across the activearea. <b>Keywords:</b>chemical vapor deposition (CVD), bipolarjunction transistor (BJT), heterojunction bipolar transistor(HBT), silicon-germanium (SiGe), epitaxy, poly-Si emitter,in situdoping, non-selective epitaxy (NSEG), loadingeffect, emissivity effect

<p>This thesis deals with the main aspects in chemical vapordeposition (CVD) of silicon (Si) and silicon-germanium (Si_1-xGe_x) films for high-speed bipolar transistors.<i>In situ</i>doping of polycrystalline silicon (poly-Si)using phosphine (PH₃) and disilane (Si₂H₆) in a low-pressure CVD reactor was investigated toestablish a poly-Si emitter fabrication process. The growthkinetics and P incorporation was studied for amorphous Si filmgrowth. Hydrogen (H) incorporated in the as-deposited films wasrelated to growth kinetics and the energy for H₂desorption was extracted. Film properties such asresistivity, mobility, carrier concentration and grain growthwere studied after crystallization using either furnaceannealing or rapid thermal annealing (RTA). In order tointegrate an epitaxial base, non-selective epitaxial growth(NSEG) of Si and SiGe in a lamp-heated single-waferreduced-pressure CVD reactor was examined. The growth kineticsfor Si epitaxy and poly-Si deposition showed a differentdependence on the deposition conditions i.e. temperature andpressure. The growth rate difference was mainly due to growthkinetics rather than wafer surface emissivity effects. However,it was observed that the growth rate for Si epitaxy and poly-Sideposition was varying during growth and the time-dependencewas attributed to wafer surface emissivity variations. A modelto describe the emissivity effects was established, taking intoconsideration kinetics and the reactor heating mechanisms suchas heat absorption, emission andconduction. Growth ratevariations in opening of different sizes (local loading) andfor different oxide surface coverage (global loading) wereinvestigated. No local loading effects were observed, whileglobal loading effects were attributed to chemical as well astemperature effects. Finally, misfit dislocations formed in theSiGe epitaxy during NSEG were found to originate from theinterface between the epitaxial and polycrystalline regions.The dislocations tended to propagate across the activearea.</p><p><b>Keywords:</b>chemical vapor deposition (CVD), bipolarjunction transistor (BJT), heterojunction bipolar transistor(HBT), silicon-germanium (SiGe), epitaxy, poly-Si emitter,<i>in situ</i>doping, non-selective epitaxy (NSEG), loadingeffect, emissivity effect</p>

Made available in DSpace on 2014-06-11T19:30:32Z (GMT). No. of bitstreams: 0 Previous issue date: 2010-01-08Bitstream added on 2014-06-13T18:40:52Z : No. of bitstreams: 1 baptista_fg_dr_ilha.pdf: 1105245 bytes, checksum: d9df8c940603a26591e01168eaac4aaa (MD5) / Conselho Nacional de Desenvolvimento Científico e Tecnológico (CNPq) / A técnica da impedância eletromecânica (E/M) tem sido amplamente pesquisada para o desenvolvimento de sistemas de SHM (Structural Health Monitoring – monitoramento de integridade estrutural) em diversas aplicações. Embora existam muitos trabalhos que indiquem a eficiência e a viabilidade dessa técnica, alguns problemas práticos em aplicações reais ainda precisam ser investigados. A medição da impedância elétrica, etapa básica da técnica, geralmente é realizada por instrumentos comerciais volumosos, pesados e de alto custo, características proibitivas para muitas aplicações. A seleção da faixa de frequência em que a impedância deve ser medida para assegurar boa sensibilidade ao dano é feita por métodos de tentativa e erro ou por metodologias que utilizam dados medidos em uma quantidade considerável de testes. Além disso, o dimensionamento dos transdutores é feito sem um embasamento teórico, independentemente das características da estrutura monitorada. Neste trabalho é proposto um sistema de medição de impedância elétrica rápido, versátil e de baixo custo que substitui com eficiência os instrumentos comerciais. A partir de um circuito eletromecânico equivalente, o efeito de carregamento do transdutor devido à estrutura monitorada foi analisado. A análise do efeito de carregamento permite dimensionar corretamente o transdutor de acordo com a estrutura monitorada e assegurar um bom desempenho do sistema. O circuito eletromecânico também foi utilizado para determinar, teoricamente, as faixas de frequência em que o transdutor tem boa sensibilidade e auxiliar na seleção da faixa de frequência adequada para a detecção de danos estruturais. Todas as metodologias propostas foram verificadas através de experimentos em estruturas de alumínio e houve uma boa concordância entre os resultados teóricos e experimentais / The electromechanical (E/M) impedance technique has been widely studied for the development of Structural Health Monitoring (SHM) systems in various applications. Although there are many studies indicating the effectiveness and feasibility of this technique, some practical issues in real applications yet should be investigated. The electrical impedance measurement, basic stage of the technique, is usually performed by bulky, heavy and expensive instruments; these features are prohibitive for many applications. The selection of the frequency range in which the electrical impedance must be measured to ensure good sensitivity for damage detection is performed by trial and error methods or by methodologies that use measured data in a considerable amount of tests. Furthermore, the design of the transducer is done without theoretical basis, regardless the characteristics of the host structure. In this work, a fast, versatile and low-cost electrical impedance measurement system was developed; the proposed system successfully replaces the conventional instruments. From an equivalent electromechanical circuit, the transducer loading effect due to the host structure was analyzed. The analysis of the loading effect allows the correct design of the transducer according to the host structure for ensure a good performance of the system. The electromechanical circuit was also used to theoretically determine the frequency ranges in which the transducer has good sensitivity and assist in the selection of the suitable frequency range for structural damage detection. All proposed methodologies were validated by experimental tests on aluminum structures and there was a good match between the theoretical and practical results

Heteroepitaxial SiGeC layers have attracted immenseattention as a material for high frequency devices duringrecent years. The unique properties of integrating carbon inSiGe are the additional freedom for strain and bandgapengineering as well as allowing more aggressive device designdue to the potential for increased thermal budget duringprocessing. This work presents different issues on epitaxialgrowth, defect density, dopant incorporation and electricalproperties of SiGeC epitaxial layers, intended for variousdevice applications. Non-selective and selective epitaxial growth of Si1-x-yGexCy(0≤x≤30, ≤y≤0.02) layershave been optimized by using high-resolution x-ray reciprocallattice mapping. The incorporation of carbon into the SiGematrix was shown to be strongly sensitive to the growthparameters. As a consequence, a much smaller epitaxial processwindow compared to SiGe epitaxy was obtained. Differentsolutions to decrease the substrate pattern dependency (loadingeffect) of SiGeC growth have also been proposed. The key pointin these methods is based on reduction of surface migration ofthe adsorbed species on the oxide. In non-selective epitaxy,this was achieved by introducing a thin silicon polycrystallineseed layer on the oxide. The thickness of this seed layer had acrucial role on both the global and local loading effect, andon the epitaxial quality. Meanwhile, in selective epitaxy,polycrystalline stripes introduced around the oxide openingsact as migration barriers and reduce the loading effecteffectively. Chemical mechanical polishing (CMP) was performedto remove the polycrystalline stripes on the oxide. Incorporation and electrical properties of boron-doped Si1-x-yGexCylayers (x=0.23 and 0.28 with y=0 and 0.005) with aboron concentration in the range of 3x1018-1x1021atoms/cm3 have also been investigated. In SiGeClayers, the active boron concentration was obtained from thestrain compensation. It was also found that the boron atomshave a tendency to locate at substitutional sites morepreferentially compared to carbon. These findings led to anestimation of the Hall scattering factor of the SiGeC layers,which showed good agreement with theoretical calculations. Keywords:Silicon germanium carbon (SiGeC), Epitaxy,Chemical vapor deposition (CVD), Loading effect, Highresolution x-ray diffraction (HRXRD), Hall measurements, Atomicforce microscopy (AFM).

Orientador: Jozué Vieira Filho / Banca: Vicente Lopes Junior / Banca: Carlos Antonio. Barros Alves / Banca: Carlos de Marqui Junior / Banca: Washington Luiz de Melo / Resumo: A técnica da impedância eletromecânica (E/M) tem sido amplamente pesquisada para o desenvolvimento de sistemas de SHM (Structural Health Monitoring - monitoramento de integridade estrutural) em diversas aplicações. Embora existam muitos trabalhos que indiquem a eficiência e a viabilidade dessa técnica, alguns problemas práticos em aplicações reais ainda precisam ser investigados. A medição da impedância elétrica, etapa básica da técnica, geralmente é realizada por instrumentos comerciais volumosos, pesados e de alto custo, características proibitivas para muitas aplicações. A seleção da faixa de frequência em que a impedância deve ser medida para assegurar boa sensibilidade ao dano é feita por métodos de tentativa e erro ou por metodologias que utilizam dados medidos em uma quantidade considerável de testes. Além disso, o dimensionamento dos transdutores é feito sem um embasamento teórico, independentemente das características da estrutura monitorada. Neste trabalho é proposto um sistema de medição de impedância elétrica rápido, versátil e de baixo custo que substitui com eficiência os instrumentos comerciais. A partir de um circuito eletromecânico equivalente, o efeito de carregamento do transdutor devido à estrutura monitorada foi analisado. A análise do efeito de carregamento permite dimensionar corretamente o transdutor de acordo com a estrutura monitorada e assegurar um bom desempenho do sistema. O circuito eletromecânico também foi utilizado para determinar, teoricamente, as faixas de frequência em que o transdutor tem boa sensibilidade e auxiliar na seleção da faixa de frequência adequada para a detecção de danos estruturais. Todas as metodologias propostas foram verificadas através de experimentos em estruturas de alumínio e houve uma boa concordância entre os resultados teóricos e experimentais / Abstract: The electromechanical (E/M) impedance technique has been widely studied for the development of Structural Health Monitoring (SHM) systems in various applications. Although there are many studies indicating the effectiveness and feasibility of this technique, some practical issues in real applications yet should be investigated. The electrical impedance measurement, basic stage of the technique, is usually performed by bulky, heavy and expensive instruments; these features are prohibitive for many applications. The selection of the frequency range in which the electrical impedance must be measured to ensure good sensitivity for damage detection is performed by trial and error methods or by methodologies that use measured data in a considerable amount of tests. Furthermore, the design of the transducer is done without theoretical basis, regardless the characteristics of the host structure. In this work, a fast, versatile and low-cost electrical impedance measurement system was developed; the proposed system successfully replaces the conventional instruments. From an equivalent electromechanical circuit, the transducer loading effect due to the host structure was analyzed. The analysis of the loading effect allows the correct design of the transducer according to the host structure for ensure a good performance of the system. The electromechanical circuit was also used to theoretically determine the frequency ranges in which the transducer has good sensitivity and assist in the selection of the suitable frequency range for structural damage detection. All proposed methodologies were validated by experimental tests on aluminum structures and there was a good match between the theoretical and practical results / Doutor