OBJECTIVE: To assess the involvement of the white matter of the brain in the pathology of Alzheimer’s disease. Using Neurite Orientation Density and Dispersion Imaging (NODDI) and the probabilistic white matter parcellation tool Tracula as a means for understanding whether alterations in the white matter underlie changes in perceived cognitive abilities across the spectrum from health aging to Alzheimer’s disease. METHOD: Data were obtained from 28 participants in the Health Outreach Program for the Elderly (HOPE) at the Boston University Alzheimer’s Disease Center (BU ADC) Clinical Core Registry. MRI scans included an MPRAGE T1 scan, multi-b shell diffusion scan and a High Angular Resolution Diffusion Imaging scan (HARDI). Scans were processed with Freesurfer v6.0 and the NODDI Python2.7 toolkit. The resulting data included the orientation dispersion index (ODI) and Fractional Anisotropy (FA) values for cortical and subcortical regions in the DKT atlas space as well as specific Tracts Constrained by Underlying Anatomy (TRACULA) measurements for 18 specific established white matter tracts. Statistical models using measures of pathway integrity (FA and ODI data) were used to assess relationships with Informant Cognitive Change Index (ICCI), self-described Cognitive Change Index (CCI), and Clinical Dementia Rating (CDR) values. RESULTS: Measures of white matter integrity within several tracts predicted ICCI and CDR well in statistical models. FA and ODI values of the bilateral superior longitudinal fasciculi, inferior longitudinal fasciculi, and the cingulum bundle tracts were all related to ICCI and CDR. None of the known tracts’ FA or ODI values were related to CCI. CONCLUSIONS: Measures of white matter pathway integrity were predictive of ICCI and CDR scores but not CCI. These finding support the notion that self-report of cognitive abilities may be compromised by alterations in insight and reinforce the need for informed study partners and clinical ratings to evaluate potential MCI and AD.

La demande croissante de toujours plus de débit pour les télécommunications entraine une augmentation de la fréquence de fonctionnement des liaisons séries. Cette demande se retrouve aussi dans les systèmes embarqués du fait de l'augmentation des performances des composants et périphériques. Afin de s'assurer que le train de données est bien réceptionné, un circuit de restitution d'horloge et de données est placé avant tout traitement du coté du récepteur. Dans ce contexte, les activités de recherche présentées dans cette thèse se concentrent sur la conception d'une CDR (Clock and Data Recovery). Nous détaillerons le comparateur de phase qui joue un rôle critique dans un tel système. Cette thèse présente un comparateur de phase ayant comme avantage d'avoir une mode de fenêtrage et une fréquence de fonctionnement réduite. La topologie spéciale utilisée pour la CDR est décrite, et la théorie relative aux oscillateurs verrouillés en injection est expliquée. L'essentiel du travail de recherche s'est concentrée sur la conception et le layout d'une restitution d'horloge dans le domaine millimétrique, à 80 Gbps. Pour cela plusieurs prototypes ont été réalisés en technologie BiCMOS 130 nm de STMicrolectronics. / The increasing bandwidth demand for telecommunication leads to an important rise of serial link operating frequencies. This demand is also present in embedded systems with the growth of devices and peripherals performances. To ensure the data stream is well recovered, a clock and data recovery (CDR) circuit is placed before any logical blocks on the receiver side. The research activities presented in this thesis are related to the design of such a CDR. The phase detector plays a critical role in the CDR circuit and is specially studied. This thesis presents a phase comparator that provides an enhancement by introducing a windowed mode and reducing its operating frequency. The used CDR has a special topology, which is described, and the injection locked oscillator theory is explained. Most of the research of this study has focused on the design and layout of a 80 Gbps CDR. Several prototypes are realized in 130 nm SiGe process from STMicroelectronics.

No description available.

This thesis explores the clock and data recovery (CDR) for the high-speed blind-sampling ADC-based receivers. This exploration results in two new CDR architectures that reduce the receiver complexity and save the ADC power and area compared to the previous work. The two proposed CDR architectures constitute the primary contributions of this thesis. The first proposed architecture, a 2x feed-forward CDR architecture, eliminates the interpolating feedback loop, used in the previously reported CDRs, in order to reduce the CDR circuit complexity. Instead of the feedback loop, the proposed architecture uses a feed-forward topology to recover the phase and data directly from the blind digital samples of the received signal. The 2x feed-forward CDR architecture was implemented and characterized in a 5 Gb/s receiver test-chip in 65 nm CMOS. The test-chip measurements confirm that the CDR successfully recovers the data with bit error rate (BER) < 10e-12 in the presence of jitter. The second proposed architecture, a fractional-sampling-rate (FSR) CDR architecture, reduces the receiver sampling rate from the typical integer rate of 2x the baud rate to a fractional rate between 2x and 1x in order to reduce the ADC power and area. This architecture employs the feed-forward topology of the first contribution of this thesis to recover the phase and data from the fractionally-spaced digital samples of the signal. To verify the proposed FSR CDR architecture, a 1.45x receiver test-chip was implemented and characterized in 65 nm CMOS. This test-chip recovers 6.875 Gb/s data from the ADC samples taken at 10 GS/s. The measurements confirm a successful data recovery in the presence of jitter with BER < 10e-12. With sampling at 1.45x, the FSR CDR architecture reduces the ADC power and area by 27.3% compared to the 2x feed-forward CDR architecture, while the overall receiver power and area are reduced by 12.5%.

This thesis explores the clock and data recovery (CDR) for the high-speed blind-sampling ADC-based receivers. This exploration results in two new CDR architectures that reduce the receiver complexity and save the ADC power and area compared to the previous work. The two proposed CDR architectures constitute the primary contributions of this thesis. The first proposed architecture, a 2x feed-forward CDR architecture, eliminates the interpolating feedback loop, used in the previously reported CDRs, in order to reduce the CDR circuit complexity. Instead of the feedback loop, the proposed architecture uses a feed-forward topology to recover the phase and data directly from the blind digital samples of the received signal. The 2x feed-forward CDR architecture was implemented and characterized in a 5 Gb/s receiver test-chip in 65 nm CMOS. The test-chip measurements confirm that the CDR successfully recovers the data with bit error rate (BER) < 10e-12 in the presence of jitter. The second proposed architecture, a fractional-sampling-rate (FSR) CDR architecture, reduces the receiver sampling rate from the typical integer rate of 2x the baud rate to a fractional rate between 2x and 1x in order to reduce the ADC power and area. This architecture employs the feed-forward topology of the first contribution of this thesis to recover the phase and data from the fractionally-spaced digital samples of the signal. To verify the proposed FSR CDR architecture, a 1.45x receiver test-chip was implemented and characterized in 65 nm CMOS. This test-chip recovers 6.875 Gb/s data from the ADC samples taken at 10 GS/s. The measurements confirm a successful data recovery in the presence of jitter with BER < 10e-12. With sampling at 1.45x, the FSR CDR architecture reduces the ADC power and area by 27.3% compared to the 2x feed-forward CDR architecture, while the overall receiver power and area are reduced by 12.5%.

Low power, high speed serial transceivers are employed in a wide range of applications ranging from chip-to-chip, backplane, and optical interconnects. Apart from being capable of handling a wide range of data rates, the transceivers should have low power consumption (mW/Gbps) and be fully integrated. This work discusses enabling techniques to implement such transceivers. Specifically, three designs: (1) a 0.5-4 Gbps serial link which uses current recycling to reduce power dissipation and (2) a 0.5-2.5 Gbps reference-less clock and data recovery circuit which uses a novel frequency detector to achieve unlimited acquisition range and (3) a 2-4 Gbps low power receiver architecture capable of resolving multiple signalling formats with a simplified XOR based phase rotating PLL will be presented. All the three circuit topologies are highly digital and aim to address the requirements of wide operating range, low power dissipation while being fully integrated. Measured results obtained from the prototypes illustrate the effectiveness of the proposed design techniques. / Graduation date: 2012 / Access restricted to the OSU Community at author's request from Dec. 2, 2011 - June 2, 2012

No description available.

Since the beginning of farming, and even before, humans have been actively modifying our environment in order to harvest biomass. With the ‘Great Acceleration’ of the industrial age, the global system of biomass harvest for food production has become a major driver of Earth system processes, and caused multi-dimensional sustainability issues which must be addressed in order to meet continued increases in demand for food and other biomass. In addition, bioenergy generation, with the subsequent storage of some or all of the carbon content of the feedstock (known as bioenergy with carbon storage or BECS), is now seen as an important tool for rebalancing the carbon cycle. This thesis has used a biomass flows modelling approach to examine possible trajectories for the socio-ecological metabolism of humanity, with a focus on fluxes of carbon contained in biomass. This approach connects social and economic drivers of biomass harvest with physical Earth systems processes such as the global carbon cycle. Meeting growing food demand in the years 2000-2050 is likely to be a significant challenge in its own right, necessitating the harvest of over 30% of terrestrial biomass. This can only be done without significant damage to natural ecosystems if large increases in efficiency and intensity of food production are achieved, or diets are altered. The production of livestock products is shown to be a major cause of inefficiency in biomass harvest, and changes to livestock demand or production are particularly powerful in ensuring a less damaging relationship with Earth system processes. If increases in efficiency are achieved, it may be possible to grow dedicated bioenergy crops, which, combined with the biomass available in waste and residue streams can be used to generate significant carbon dioxide removal (CDR) fluxes via BECS. Following this strategy it is possible to have a non-trivial effect on atmospheric CO2 concentration by 2050. Increasing the intensity of biomass harvest, particularly when low intensity pasture is replaced with intense bioenergy cropping, also has significant implications for ecological energy flows, and the potential trade-off between protecting biodiversity and growing bioenergy crops to mitigate climate change is also discussed. This body of work presents several interesting areas of potential conflict in different drivers of biomass harvest, and suggestions are made for ways in which to develop the approach in order to explore them.

Les télomères sont des complexes nucléoprotéiques localisés à l'extrémité des chromosomes des cellules<br />eucaryotes. L'ADN télomérique humain contient entre 500 et 3000 repétitions de la séquence d(T2AG3)n (brin-G) et de son brin complémentaire C3TA2 (brin-C). Le brin G est terminé par une extrémité simple brin contenant de 50 à 200 nucléotides. Les télomères jouent des rôles essentiels au niveau cellulaire en permnettant la protection des chromosomes.<br />Un modèle proposé pour expliquer le rôle protecteur des télomères est le modèle de la boucle-T (télomérique) / boucle-D (déplacement). Dans ce modèle, on observe le repliement de I'ADN télomérique double brin et I'insertion de la partie simple brin dans la partie double brin. La formation de ces boucles fait intervenir, directement ou indirectement, denombreuses protéines comme les protéines TRF1 et TRF2. Néanmoins les mécanismes moléculaires et notamment le rôle de la protéine TRF2 dans la formation de ces boucles restent spéculatifs.<br />Le travail de thèse présenté dans ce manuscrit expose l'étude par Résonance Magnétique Nucléaire du domaine<br />de fixation à I'ADN de la protéine TRF2 (domaine Myb) et de ses interactions avec-l'ADN télomérique ainsi que<br />l'étude de modèles de boucles-D.<br />Après la détermination de la structure tridimensionnelle et l'étude de la dynamique interne du domaine Myb de<br />TRF2, nous avons réalisé l'étude des interactions du domaine Myb avec I'ADN télomérique. Ainsi, deux complexes entre le domaine Myb de TRF2 et I'ADN télomérique ont été étudiés par RMN et ont permis de mieux comprendre le rôle du domaine Myb en montrant sa grande spécificité pour I'ADN télômérique double brin. Ensuite quatre modèles de boucles D différents ont été étudiés par RMN afin d'en déterminer les structures tridimensionnelles.

Advances in technology and the introduction of high speed processors have increased the demand for fast, compact and commercial methods for transferring large amounts of data. The next generation of the communication access network will use optical fiber as a media for data transmission to the subscriber. In optical data or chip-to-chip data communication, the continuous received data needs to be converted to discrete data. For the conversion, a synchronous clock and data are required. A clock and data recovery (CDR) circuit recovers the phase information from the data and generates the in-phase clock and data. In this dissertation, two clock and data recovery circuits for Giga-bits per second (Gbps) serial data communication are designed and fabricated in 180nm and 90nm CMOS technology. The primary objective was to reduce the circuit power dissipation for multi-channel data communication applications. The power saving is achieved using low swing voltage signaling scheme. Furthermore, a novel low input swing Alexander phase detector is introduced. The proposed phase detector reduces the power consumption at the transmitter and receiver blocks. The circuit demonstrates a low power dissipation of 340µW/Gbps in 90nm CMOS technology. The CDR is able to recover the input signal swing of 35mVp. The peak-to-peak jitter is 21ps and RMS jitter is 2.5ps. Total core area excluding pads is approximately 0.01mm2.